67273393b1
Using GEP to index into a vector is not disallowed, but not recommended. The SPIR-V backend needs to generate structured access into types, which is impossible with an untyped GEP instruction unless we add more info to the IR. Finding a solution is a work-in-progress, but in the meantime, we'd like to reduce the amount of failures. Preventing this optimizations from rewritting extract/insert instructions into a GEP helps us lower more code to SPIR-V. This change should be OK as it's only active when targeting SPIR-V and disabling a non-recommended transformation. Related to #145002
69 lines
2.7 KiB
C++
69 lines
2.7 KiB
C++
//===- SPIRVTargetTransformInfo.h - SPIR-V specific TTI ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// \file
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// This file contains a TargetTransformInfoImplBase conforming object specific
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// to the SPIRV target machine. It uses the target's detailed information to
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// provide more precise answers to certain TTI queries, while letting the
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// target independent and default TTI implementations handle the rest.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SPIRV_SPIRVTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_SPIRV_SPIRVTARGETTRANSFORMINFO_H
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#include "SPIRV.h"
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#include "SPIRVTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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namespace llvm {
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class SPIRVTTIImpl final : public BasicTTIImplBase<SPIRVTTIImpl> {
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using BaseT = BasicTTIImplBase<SPIRVTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const SPIRVSubtarget *ST;
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const SPIRVTargetLowering *TLI;
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const TargetSubtargetInfo *getST() const { return ST; }
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const SPIRVTargetLowering *getTLI() const { return TLI; }
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public:
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explicit SPIRVTTIImpl(const SPIRVTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) const override {
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// SPIR-V natively supports OpBitcount, per 3.53.14 in the spec, as such it
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// is reasonable to assume the Op is fast / preferable to the expanded loop.
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// Furthermore, this prevents information being lost if transforms are
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// applied to SPIR-V before lowering to a concrete target.
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if (!isPowerOf2_32(TyWidth) || TyWidth > 64)
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return TTI::PSK_Software; // Arbitrary bit-width INT is not core SPIR-V.
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return TTI::PSK_FastHardware;
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}
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unsigned getFlatAddressSpace() const override {
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// Clang has 2 distinct address space maps. One where
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// default=4=Generic, and one with default=0=Function. This depends on the
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// environment.
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return ST->isShader() ? 0 : 4;
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}
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bool collectFlatAddressOperands(SmallVectorImpl<int> &OpIndexes,
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Intrinsic::ID IID) const override;
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Value *rewriteIntrinsicWithAddressSpace(IntrinsicInst *II, Value *OldV,
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Value *NewV) const override;
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bool allowVectorElementIndexingUsingGEP() const override { return false; }
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};
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_SPIRV_SPIRVTARGETTRANSFORMINFO_H
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