9e9907f1cf
Similar to 806761a7629df268c8aed49657aeccffa6bca449. For IR files without a target triple, -mtriple= specifies the full target triple while -march= merely sets the architecture part of the default target triple, leaving a target triple which may not make sense, e.g. amdgpu-apple-darwin. Therefore, -march= is error-prone and not recommended for tests without a target triple. The issue has been benign as we recognize $unknown-apple-darwin as ELF instead of rejecting it outrightly. This patch changes AMDGPU tests to not rely on the default OS/environment components. Tests that need fixes are not changed: ``` LLVM :: CodeGen/AMDGPU/fabs.f64.ll LLVM :: CodeGen/AMDGPU/fabs.ll LLVM :: CodeGen/AMDGPU/floor.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll LLVM :: CodeGen/AMDGPU/fneg-fabs.ll LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll LLVM :: CodeGen/AMDGPU/schedule-if-2.ll ```
67 lines
2.4 KiB
LLVM
67 lines
2.4 KiB
LLVM
; Function Attrs: nounwind
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; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s
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;
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; CFG flattening should use parallel-or to generate branch conditions and
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; then merge if-regions with the same bodies.
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; FIXME: For some reason having the allocas here allowed the flatten cfg pass
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; to do its transformation, however now that we are using local memory for
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; allocas, the transformation isn't happening.
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; XFAIL: *
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;
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; CHECK: OR_INT
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; CHECK-NEXT: OR_INT
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; CHECK-NEXT: OR_INT
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define amdgpu_kernel void @_Z9chk1D_512v() #0 {
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entry:
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%a0 = alloca i32, align 4, addrspace(5)
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%b0 = alloca i32, align 4, addrspace(5)
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%c0 = alloca i32, align 4, addrspace(5)
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%d0 = alloca i32, align 4, addrspace(5)
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%a1 = alloca i32, align 4, addrspace(5)
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%b1 = alloca i32, align 4, addrspace(5)
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%c1 = alloca i32, align 4, addrspace(5)
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%d1 = alloca i32, align 4, addrspace(5)
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%data = alloca i32, align 4, addrspace(5)
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%0 = load i32, ptr addrspace(5) %a0, align 4
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%1 = load i32, ptr addrspace(5) %b0, align 4
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%cmp = icmp ne i32 %0, %1
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br i1 %cmp, label %land.lhs.true, label %if.else
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land.lhs.true: ; preds = %entry
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%2 = load i32, ptr addrspace(5) %c0, align 4
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%3 = load i32, ptr addrspace(5) %d0, align 4
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%cmp1 = icmp ne i32 %2, %3
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br i1 %cmp1, label %if.then, label %if.else
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if.then: ; preds = %land.lhs.true
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br label %if.end
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if.else: ; preds = %land.lhs.true, %entry
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store i32 1, ptr addrspace(5) %data, align 4
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br label %if.end
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if.end: ; preds = %if.else, %if.then
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%4 = load i32, ptr addrspace(5) %a1, align 4
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%5 = load i32, ptr addrspace(5) %b1, align 4
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%cmp2 = icmp ne i32 %4, %5
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br i1 %cmp2, label %land.lhs.true3, label %if.else6
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land.lhs.true3: ; preds = %if.end
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%6 = load i32, ptr addrspace(5) %c1, align 4
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%7 = load i32, ptr addrspace(5) %d1, align 4
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%cmp4 = icmp ne i32 %6, %7
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br i1 %cmp4, label %if.then5, label %if.else6
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if.then5: ; preds = %land.lhs.true3
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br label %if.end7
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if.else6: ; preds = %land.lhs.true3, %if.end
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store i32 1, ptr addrspace(5) %data, align 4
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br label %if.end7
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if.end7: ; preds = %if.else6, %if.then5
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ret void
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}
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