ba1d901967
The input is an integer which can't be NAN so the NV(invalid) exception can't be raised. The conversion is exact so it can't raise NX(inexact), UF(underflow), or OF(overflow). The instructions are not divide so they can't raise DZ(divide by zero). Fixes #133192.
105 lines
4.1 KiB
LLVM
105 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f,+d -stop-after=finalize-isel < %s \
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; RUN: -target-abi=ilp32d | FileCheck -check-prefixes=RV32IF %s
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; RUN: llc -mtriple=riscv64 -mattr=+f,+d -stop-after=finalize-isel < %s \
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; RUN: -target-abi=lp64d | FileCheck -check-prefixes=RV64IF %s
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; Make sure an implicit FRM dependency is added to instructions with dynamic
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; rounding.
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define float @fadd_s(float %a, float %b) nounwind {
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; RV32IF-LABEL: name: fadd_s
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; RV32IF: bb.0 (%ir-block.0):
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; RV32IF-NEXT: liveins: $f10_f, $f11_f
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; RV32IF-NEXT: {{ $}}
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; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f
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; RV32IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
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; RV32IF-NEXT: %2:fpr32 = nofpexcept FADD_S [[COPY1]], [[COPY]], 7, implicit $frm
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; RV32IF-NEXT: $f10_f = COPY %2
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; RV32IF-NEXT: PseudoRET implicit $f10_f
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; RV64IF-LABEL: name: fadd_s
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; RV64IF: bb.0 (%ir-block.0):
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; RV64IF-NEXT: liveins: $f10_f, $f11_f
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; RV64IF-NEXT: {{ $}}
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; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f
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; RV64IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
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; RV64IF-NEXT: %2:fpr32 = nofpexcept FADD_S [[COPY1]], [[COPY]], 7, implicit $frm
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; RV64IF-NEXT: $f10_f = COPY %2
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; RV64IF-NEXT: PseudoRET implicit $f10_f
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%1 = fadd float %a, %b
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ret float %1
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}
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declare float @llvm.fma.f32(float, float, float)
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define float @fmadd_s(float %a, float %b, float %c) nounwind {
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; RV32IF-LABEL: name: fmadd_s
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; RV32IF: bb.0 (%ir-block.0):
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; RV32IF-NEXT: liveins: $f10_f, $f11_f, $f12_f
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; RV32IF-NEXT: {{ $}}
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; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f12_f
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; RV32IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; RV32IF-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f
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; RV32IF-NEXT: %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm
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; RV32IF-NEXT: $f10_f = COPY %3
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; RV32IF-NEXT: PseudoRET implicit $f10_f
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; RV64IF-LABEL: name: fmadd_s
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; RV64IF: bb.0 (%ir-block.0):
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; RV64IF-NEXT: liveins: $f10_f, $f11_f, $f12_f
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; RV64IF-NEXT: {{ $}}
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; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f12_f
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; RV64IF-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f11_f
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; RV64IF-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY $f10_f
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; RV64IF-NEXT: %3:fpr32 = nofpexcept FMADD_S [[COPY2]], [[COPY1]], [[COPY]], 7, implicit $frm
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; RV64IF-NEXT: $f10_f = COPY %3
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; RV64IF-NEXT: PseudoRET implicit $f10_f
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%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
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ret float %1
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}
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; This uses rtz instead of dyn rounding mode so shouldn't have an FRM dependncy.
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define i32 @fcvt_w_s(float %a) nounwind {
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; RV32IF-LABEL: name: fcvt_w_s
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; RV32IF: bb.0 (%ir-block.0):
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; RV32IF-NEXT: liveins: $f10_f
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; RV32IF-NEXT: {{ $}}
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; RV32IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; RV32IF-NEXT: %1:gpr = nofpexcept FCVT_W_S [[COPY]], 1
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; RV32IF-NEXT: $x10 = COPY %1
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; RV32IF-NEXT: PseudoRET implicit $x10
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; RV64IF-LABEL: name: fcvt_w_s
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; RV64IF: bb.0 (%ir-block.0):
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; RV64IF-NEXT: liveins: $f10_f
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; RV64IF-NEXT: {{ $}}
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; RV64IF-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f10_f
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; RV64IF-NEXT: %1:gpr = nofpexcept FCVT_W_S [[COPY]], 1
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; RV64IF-NEXT: $x10 = COPY %1
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; RV64IF-NEXT: PseudoRET implicit $x10
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%1 = fptosi float %a to i32
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ret i32 %1
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}
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; This doesn't use a rounding mode since i32 can be represented exactly as a
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; double.
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define double @fcvt_d_w(i32 %a) nounwind {
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; RV32IF-LABEL: name: fcvt_d_w
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; RV32IF: bb.0 (%ir-block.0):
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; RV32IF-NEXT: liveins: $x10
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; RV32IF-NEXT: {{ $}}
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; RV32IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV32IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
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; RV32IF-NEXT: $f10_d = COPY [[FCVT_D_W]]
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; RV32IF-NEXT: PseudoRET implicit $f10_d
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;
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; RV64IF-LABEL: name: fcvt_d_w
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; RV64IF: bb.0 (%ir-block.0):
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; RV64IF-NEXT: liveins: $x10
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; RV64IF-NEXT: {{ $}}
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; RV64IF-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
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; RV64IF-NEXT: [[FCVT_D_W:%[0-9]+]]:fpr64 = FCVT_D_W [[COPY]], 0
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; RV64IF-NEXT: $f10_d = COPY [[FCVT_D_W]]
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; RV64IF-NEXT: PseudoRET implicit $f10_d
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%1 = sitofp i32 %a to double
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ret double %1
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}
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