3787fbf040
This follows up #115495 by enabling merging of external globals by default, which had been left as a next step in order to make the previous change more incremental and so we can more easily narrow down on any identified regressions. Enabling merging of external globals matches what Arm does (for non mach-o targets), though AArch64 doesn't as there were [some concerns](https://reviews.llvm.org/D61947) it might cause regressions in some cases. See https://github.com/llvm/llvm-project/pull/117880 for benchmark figures and discussion.
49 lines
1.8 KiB
LLVM
49 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -global-merge-on-external=false \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -global-merge-on-external=false \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=CHECK-WEXTERN %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=CHECK-WEXTERN %s
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@ig1 = internal global i32 0, align 4
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@ig2 = internal global i32 0, align 4
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@eg1 = dso_local global i32 0, align 4
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@eg2 = dso_local global i32 0, align 4
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; TODO: It would be better for code size to alter the first store below by
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; first fully materialising .L_MergedGlobals in a1 and then storing to it with
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; a 0 offset.
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define void @f1(i32 %a) nounwind {
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; CHECK-LABEL: f1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a1, %hi(eg1)
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; CHECK-NEXT: sw a0, %lo(eg1)(a1)
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; CHECK-NEXT: lui a1, %hi(.L_MergedGlobals)
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; CHECK-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
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; CHECK-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
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; CHECK-NEXT: sw a0, 4(a1)
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; CHECK-NEXT: lui a1, %hi(eg2)
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; CHECK-NEXT: sw a0, %lo(eg2)(a1)
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; CHECK-NEXT: ret
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;
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; CHECK-WEXTERN-LABEL: f1:
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; CHECK-WEXTERN: # %bb.0:
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; CHECK-WEXTERN-NEXT: lui a1, %hi(.L_MergedGlobals)
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; CHECK-WEXTERN-NEXT: sw a0, %lo(.L_MergedGlobals)(a1)
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; CHECK-WEXTERN-NEXT: addi a1, a1, %lo(.L_MergedGlobals)
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; CHECK-WEXTERN-NEXT: sw a0, 4(a1)
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; CHECK-WEXTERN-NEXT: sw a0, 8(a1)
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; CHECK-WEXTERN-NEXT: sw a0, 12(a1)
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; CHECK-WEXTERN-NEXT: ret
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store i32 %a, ptr @ig1, align 4
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store i32 %a, ptr @ig2, align 4
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store i32 %a, ptr @eg1, align 4
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store i32 %a, ptr @eg2, align 4
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ret void
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}
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