Craig Topper 9067070d91
[RISCV] Re-separate unaligned scalar and vector memory features in the backend. (#88954)
This is largely a revert of commit
e81796671890b59c110f8e41adc7ca26f8484d20.

As #88029 shows, there exists hardware that only supports unaligned
scalar.

I'm leaving how this gets exposed to the clang interface to a future
patch.
2024-04-16 15:40:32 -07:00

22 lines
720 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem | FileCheck %s
define void @foo_set(ptr nocapture noundef %a, i32 noundef %v) {
; CHECK-LABEL: foo_set:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: srli a2, a1, 8
; CHECK-NEXT: sb a1, 3(a0)
; CHECK-NEXT: sb a2, 4(a0)
; CHECK-NEXT: ret
entry:
%bf.load = load i96, ptr %a, align 1
%0 = and i32 %v, 65535
%bf.value = zext i32 %0 to i96
%bf.shl = shl nuw nsw i96 %bf.value, 24
%bf.clear = and i96 %bf.load, -1099494850561
%bf.set = or i96 %bf.clear, %bf.shl
store i96 %bf.set, ptr %a, align 1
ret void
}