22deaa5a1a
Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR delegate to the helper methods which take an extra ARM_ShifterType parameter. The opcodes tables have not been updated yet to reflect these new entries. llvm-svn: 125633
100 lines
3.6 KiB
C++
100 lines
3.6 KiB
C++
//===-- lldb_ARMDefines.h ---------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_ARMDefines_h_
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#define lldb_ARMDefines_h_
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// Common defintions for the ARM/Thumb Instruction Set Architecture.
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namespace lldb_private {
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// ARM shifter types
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typedef enum
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{
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SRType_LSL,
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SRType_LSR,
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SRType_ASR,
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SRType_ROR,
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SRType_RRX
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} ARM_ShifterType;
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// ARM conditions // Meaning (integer) Meaning (floating-point) Condition flags
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#define COND_EQ 0x0 // Equal Equal Z == 1
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#define COND_NE 0x1 // Not equal Not equal, or unordered Z == 0
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#define COND_CS 0x2 // Carry set >, ==, or unordered C == 1
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#define COND_HS 0x2
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#define COND_CC 0x3 // Carry clear Less than C == 0
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#define COND_LO 0x3
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#define COND_MI 0x4 // Minus, negative Less than N == 1
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#define COND_PL 0x5 // Plus, positive or zero >, ==, or unordered N == 0
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#define COND_VS 0x6 // Overflow Unordered V == 1
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#define COND_VC 0x7 // No overflow Not unordered V == 0
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#define COND_HI 0x8 // Unsigned higher Greater than, or unordered C == 1 and Z == 0
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#define COND_LS 0x9 // Unsigned lower or same Less than or equal C == 0 or Z == 1
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#define COND_GE 0xA // Greater than or equal Greater than or equal N == V
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#define COND_LT 0xB // Less than Less than, or unordered N != V
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#define COND_GT 0xC // Greater than Greater than Z == 0 and N == V
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#define COND_LE 0xD // Less than or equal <, ==, or unordered Z == 1 or N != V
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#define COND_AL 0xE // Always (unconditional) Always (unconditional) Any
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#define COND_UNCOND 0xF
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static inline const char *ARMCondCodeToString(uint32_t CC)
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{
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switch (CC) {
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default: assert(0 && "Unknown condition code");
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case COND_EQ: return "eq";
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case COND_NE: return "ne";
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case COND_HS: return "hs";
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case COND_LO: return "lo";
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case COND_MI: return "mi";
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case COND_PL: return "pl";
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case COND_VS: return "vs";
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case COND_VC: return "vc";
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case COND_HI: return "hi";
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case COND_LS: return "ls";
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case COND_GE: return "ge";
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case COND_LT: return "lt";
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case COND_GT: return "gt";
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case COND_LE: return "le";
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case COND_AL: return "al";
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}
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}
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// Bit positions for CPSR
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#define CPSR_T 5
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#define CPSR_F 6
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#define CPSR_I 7
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#define CPSR_A 8
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#define CPSR_E 9
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#define CPSR_J 24
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#define CPSR_Q 27
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#define CPSR_V 28
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#define CPSR_C 29
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#define CPSR_Z 30
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#define CPSR_N 31
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// Masks for CPSR
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#define MASK_CPSR_MODE_MASK (0x0000001fu)
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#define MASK_CPSR_T (1u << CPSR_T)
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#define MASK_CPSR_F (1u << CPSR_F)
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#define MASK_CPSR_I (1u << CPSR_I)
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#define MASK_CPSR_A (1u << CPSR_A)
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#define MASK_CPSR_E (1u << CPSR_E)
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#define MASK_CPSR_GE_MASK (0x000f0000u)
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#define MASK_CPSR_J (1u << CPSR_J)
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#define MASK_CPSR_Q (1u << CPSR_Q)
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#define MASK_CPSR_V (1u << CPSR_V)
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#define MASK_CPSR_C (1u << CPSR_C)
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#define MASK_CPSR_Z (1u << CPSR_Z)
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#define MASK_CPSR_N (1u << CPSR_N)
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} // namespace lldb_private
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#endif // lldb_ARMDefines_h_
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