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llvm-project/llvm/test/Transforms/LoopVectorize/X86
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Kerry McLaughlin 6f16ee5e14 Revert "[LoopVectorize] Extract the last lane from a uniform store" 
This reverts commit 0d748b4d32cbddf58a1ff83f3ff178ec1ad49edc.
This is causing some failures when building Spec2017 with scalable
vectors. Reverting to investigate.
2021-11-10 11:21:19 +00:00
..
already-vectorized.ll
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avx1.ll
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avx512.ll
[LV] Let selectVectorizationFactor reason directly on VectorizationFactor.
2021-04-20 09:54:45 +01:00
consecutive-ptr-cg-bug.ll
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consecutive-ptr-uniforms.ll
[VPlan] Merge predicated-triangle regions, after sinking.
2021-06-28 11:10:38 +01:00
constant-fold.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
constant-vector-operand.ll
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conversion-cost.ll
Revert "[NFC] IRBuilderBase::CreateAdd(): place constant onto RHS"
2021-10-27 22:21:37 +03:00
cost-model-assert.ll
Revert "[LoopVectorize] Extract the last lane from a uniform store"
2021-11-10 11:21:19 +00:00
cost-model.ll
[X86][LV] X86 does *not* prefer vectorized addressing
2021-10-16 12:32:18 +03:00
float-induction-x86.ll
[opt] Directly translate -O# to -passes='default<O#>'
2021-10-18 16:48:10 -07:00
fneg-cost.ll
[CostModel][X86] Improve fneg costs
2021-05-21 17:23:45 +01:00
fp32_to_uint32-cost-model.ll
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fp64_to_uint32-cost-model.ll
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fp80-widest-type.ll
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fp_to_sint8-cost-model.ll
[CostModel][X86] Adjust fptosi/fptoui SSE/AVX legalized costs based on llvm-mca reports.
2021-07-12 20:38:25 +01:00
funclet.ll
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gather_scatter.ll
Reapply 5ec2386 "Reapply db28934 "[IndVars] Pass TTI to replaceCongruentIVs""
2021-11-10 17:36:14 +07:00
gather-cost.ll
[NFC][X86][LoopVectorize] Autogenerate check lines in a few tests for ease of updating
2021-10-06 22:54:15 +03:00
gather-vs-interleave.ll
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gcc-examples.ll
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illegal-parallel-loop-uniform-write.ll
Revert "[LoopVectorize] Extract the last lane from a uniform store"
2021-11-10 11:21:19 +00:00
imprecise-through-phis.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
int128_no_gather.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
interleave_short_tc.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
interleaved-accesses-large-gap.ll
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interleaved-accesses-waw-dependency.ll
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interleaving.ll
[TTI][X86] Add SSE2 sub-128bit vXi16/32 and v2i64 stride 2 interleaved load costs
2021-10-16 16:21:45 +01:00
intrinsiccost.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
invariant-load-gather.ll
[LoopUtils] Fix incorrect RT check bounds of loop-invariant mem accesses
2021-07-19 19:38:24 +08:00
invariant-store-vectorization.ll
[LoopUtils] Fix incorrect RT check bounds of loop-invariant mem accesses
2021-07-19 19:38:24 +08:00
libm-vector-calls-finite.ll
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libm-vector-calls-VF2-VF8.ll
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libm-vector-calls.ll
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lit.local.cfg
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load-deref-pred.ll
Revert "[NFC] IRBuilderBase::CreateAdd(): place constant onto RHS"
2021-10-27 22:21:37 +03:00
masked_load_store.ll
[LoopUtils] Simplify addRuntimeCheck to return a single value.
2021-10-18 18:03:09 +01:00
max-mstore.ll
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metadata-enable.ll
[opt] Directly translate -O# to -passes='default<O#>'
2021-10-18 16:48:10 -07:00
min-trip-count-switch.ll
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mul_slm_16bit.ll
[CostModel][X86] Adjust vXi32 multiply costs if it can be performed using PMADDWD
2021-09-25 16:28:48 +01:00
no_fpmath_with_hotness.ll
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no_fpmath.ll
[LV] Consider Loop Unroll Hints When Making Interleave Decisions
2021-04-28 17:27:52 -04:00
no-vector.ll
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nontemporal.ll
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optsize.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
outer_loop_test1_no_explicit_vect_width.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
parallel-loops-after-reg2mem.ll
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parallel-loops.ll
[X86][LV] X86 does *not* prefer vectorized addressing
2021-10-16 12:32:18 +03:00
pointer-runtime-checks-unprofitable.ll
[LV] Add tests where rt checks may make vectorization unprofitable.
2021-09-27 10:32:28 +01:00
powof2div.ll
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pr23997.ll
Regen some autogen tests to account for format change
2021-10-28 09:22:20 -07:00
pr34438.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
pr35432.ll
Revert rest of IRBuilderBase's short-circuiting folds
2021-10-28 02:15:14 +03:00
pr36524.ll
Revert "[NFC] IRBuilderBase::CreateAdd(): place constant onto RHS"
2021-10-27 22:21:37 +03:00
pr39160.ll
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pr42674.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
pr47437.ll
[TTI][X86] Add v8i16 -> 2 x v4i16 stride 2 interleaved load costs
2021-10-16 17:28:07 +01:00
pr48340.ll
[NFC] Re-harden test/Transforms/LoopVectorize/X86/pr48340.ll
2021-10-22 15:07:53 +03:00
propagate-metadata.ll
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ptr-indvar-crash.ll
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rauw-bug.ll
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reduction-crash.ll
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reduction-fastmath.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
reduction-small-size.ll
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redundant-vf2-cost.ll
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reg-usage-debug.ll
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reg-usage.ll
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register-assumption.ll
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runtime-limit.ll
Recommit "[LV] Move runtime pointer size check to LVP::plan()."
2021-03-29 16:14:27 +01:00
scatter_crash.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
slm-no-vectorize.ll
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small-size.ll
[VPlan] Merge predicated-triangle regions, after sinking.
2021-06-28 11:10:38 +01:00
strided_load_cost.ll
[NFC][X86][LoopVectorize] Autogenerate check lines in a few tests for ease of updating
2021-10-06 22:54:15 +03:00
struct-store.ll
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svml-calls-finite.ll
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svml-calls.ll
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tail_folding_and_assume_safety.ll
[LV] Parallel annotated loop does not imply all loads can be hoisted.
2021-06-10 23:37:57 +02:00
tail_loop_folding.ll
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tripcount.ll
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uint64_to_fp64-cost-model.ll
[CostModel][X86] Adjust uitofp(vXi64) SSE/AVX legalized costs based on llvm-mca reports.
2021-07-02 13:09:00 +01:00
uniform_load.ll
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uniform_mem_op.ll
Revert "[LoopVectorize] Extract the last lane from a uniform store"
2021-11-10 11:21:19 +00:00
uniform-phi.ll
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uniformshift.ll
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unroll_selection.ll
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unroll-pm.ll
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unroll-small-loops.ll
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veclib-calls.ll
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vect.omp.force.ll
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vect.omp.force.small-tc.ll
[LV] Mark increment of main vector loop induction variable as NUW.
2021-06-07 10:47:52 +01:00
vector_max_bandwidth.ll
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vector_ptr_load_store.ll
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vector-scalar-select-cost.ll
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vectorization-remarks-loopid-dbg.ll
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vectorization-remarks-missed.ll
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vectorization-remarks-profitable.ll
Revert "[NFC] remove explicit default value for strboolattr attribute in tests"
2021-05-24 19:43:40 +02:00
vectorization-remarks.ll
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vectorize-only-for-real.ll
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x86_fp80-interleaved-access.ll
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x86_fp80-vector-store.ll
[opt] Directly translate -O# to -passes='default<O#>'
2021-10-18 16:48:10 -07:00
x86-interleaved-accesses-masked-group.ll
[LV] Fix 2nd crash for reverse interleaved groups under mask/fold-tail.
2021-10-12 21:44:42 +03:00
x86-interleaved-store-accesses-with-gaps.ll
Revert rG1c9bec727ab5c53fa060560dc8d346a911142170 : [InstCombine] Fold (gep (oneuse(gep Ptr, Idx0)), Idx1) -> (gep Ptr, (add Idx0, Idx1)) (PR51069)
2021-08-23 21:09:26 +01:00
x86-pr39099.ll
[VPlan] Merge predicated-triangle regions, after sinking.
2021-06-28 11:10:38 +01:00
x86-predication.ll
[VPlan] Merge predicated-triangle regions, after sinking.
2021-06-28 11:10:38 +01:00