fc5ef57c7d
:q! This diff is massive, but it's because it connects the client with lldb-server and also ensures that the postmortem case works. - Flatten the postmortem trace schema. The reason is that the schema has become quite complex due to the new multicore case, which defeats the original purpose of having a schema that could work for every trace plug-in. At this point, it's better that each trace plug-in defines it's own full schema. This means that the only common field is "type". -- Because of this new approach, I merged the "common" trace load and saving functionalities into the IntelPT one. This simplified the code quite a bit. If we eventually implement another trace plug-in, we can see then what we could reuse. -- The new schema, which is flattened, has now better comments and is parsed better. A change I did was to disallow hex addresses, because they are a bit error prone. I'm asking now to print the address in decimal. -- Renamed "intel" to "GenuineIntel" in the schema because that's what you see in /proc/cpuinfo. - Implemented reading the context switch trace data buffer. I had to do some refactors to do that cleanly. -- A major change that I did here was to simplify the perf_event circular buffer reading logic. It was too complex. Maybe the original Intel author had something different in mind. - Implemented all the necessary bits to read trace.json files with per-core data. - Implemented all the necessary bits to save to disk per-core trace session. - Added a test that ensures that parsing and saving to disk works. Differential Revision: https://reviews.llvm.org/D126015
114 lines
4.0 KiB
Python
114 lines
4.0 KiB
Python
import lldb
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from intelpt_testcase import *
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from lldbsuite.test.lldbtest import *
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from lldbsuite.test import lldbutil
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from lldbsuite.test.decorators import *
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class TestTraceLoad(TraceIntelPTTestCaseBase):
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mydir = TestBase.compute_mydir(__file__)
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NO_DEBUG_INFO_TESTCASE = True
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def testLoadTrace(self):
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src_dir = self.getSourceDir()
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trace_definition_file = os.path.join(src_dir, "intelpt-trace", "trace.json")
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self.expect("trace load -v " + trace_definition_file, substrs=["intel-pt"])
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target = self.dbg.GetSelectedTarget()
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process = target.GetProcess()
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self.assertEqual(process.GetProcessID(), 1234)
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self.assertEqual(process.GetNumThreads(), 1)
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self.assertEqual(process.GetThreadAtIndex(0).GetThreadID(), 3842849)
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self.assertEqual(target.GetNumModules(), 1)
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module = target.GetModuleAtIndex(0)
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path = module.GetFileSpec()
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self.assertEqual(path.fullpath, os.path.join(src_dir, "intelpt-trace", "a.out"))
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self.assertGreater(module.GetNumSections(), 0)
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self.assertEqual(module.GetSectionAtIndex(0).GetFileAddress(), 0x400000)
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self.assertEqual("6AA9A4E2-6F28-2F33-377D-59FECE874C71-5B41261A", module.GetUUIDString())
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# check that the Process and Thread objects were created correctly
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self.expect("thread info", substrs=["tid = 3842849"])
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self.expect("thread list", substrs=["Process 1234 stopped", "tid = 3842849"])
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self.expect("thread trace dump info", substrs=['''Trace technology: intel-pt
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thread #1: tid = 3842849
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Total number of instructions: 21
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Memory usage:
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Raw trace size: 4 KiB
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Total approximate memory usage (excluding raw trace): 1.27 KiB
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Average memory usage per instruction (excluding raw trace): 61.76 bytes
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Timing:
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Decoding instructions: ''', '''s
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Events:
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Number of instructions with events: 1
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Number of individual events: 1
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paused: 1
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Errors:
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Number of TSC decoding errors: 0'''])
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def testLoadInvalidTraces(self):
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src_dir = self.getSourceDir()
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# We test first an invalid type
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self.expect("trace load -v " + os.path.join(src_dir, "intelpt-trace", "trace_bad.json"), error=True,
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substrs=['''error: expected object at traceSession.processes[0]
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Context:
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{
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"cpuInfo": { ... },
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"processes": [
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/* error: expected object */
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123
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],
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"type": "intel-pt"
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}
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Schema:
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{
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"type": "intel-pt",
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"cpuInfo": {
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// CPU information gotten from, for example, /proc/cpuinfo.
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"vendor": "GenuineIntel" | "unknown",
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"family": integer,
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"model": integer,
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"stepping": integer
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},'''])
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# Now we test a missing field in the global session file
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self.expect("trace load -v " + os.path.join(src_dir, "intelpt-trace", "trace_bad2.json"), error=True,
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substrs=['error: missing value at traceSession.processes[1].triple', "Context", "Schema"])
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# Now we test a missing field in the intel-pt settings
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self.expect("trace load -v " + os.path.join(src_dir, "intelpt-trace", "trace_bad4.json"), error=True,
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substrs=['''error: missing value at traceSession.cpuInfo.family
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Context:
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{
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"cpuInfo": /* error: missing value */ {
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"model": 79,
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"stepping": 1,
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"vendor": "GenuineIntel"
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},
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"processes": [],
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"type": "intel-pt"
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}''', "Schema"])
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# Now we test an incorrect load address in the intel-pt settings
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self.expect("trace load -v " + os.path.join(src_dir, "intelpt-trace", "trace_bad5.json"), error=True,
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substrs=['error: missing value at traceSession.processes[1].pid', "Schema"])
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# The following wrong schema will have a valid target and an invalid one. In the case of failure,
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# no targets should be created.
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self.assertEqual(self.dbg.GetNumTargets(), 0)
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self.expect("trace load -v " + os.path.join(src_dir, "intelpt-trace", "trace_bad3.json"), error=True,
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substrs=['error: missing value at traceSession.processes[1].pid'])
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self.assertEqual(self.dbg.GetNumTargets(), 0)
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