Zoran Jovanovic f4f5f1e272 [mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions ...

Differential Revision: http://reviews.llvm.org/D5933

llvm-svn: 221352

2014-11-05 15:46:53 +00:00

..

AArch64

[AArch64] Use the correct register class for ORR.

2014-11-04 22:20:07 +00:00

ARM

ARM: try to add extra CS-register whenever stack alignment >= 8.

2014-11-05 00:27:20 +00:00

CPP

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Generic

Revert "Revert "DI: Fold constant arguments into a single MDString""

2014-10-03 20:01:09 +00:00

Hexagon

Handle ctor/init_array initialization.

2014-11-03 14:56:05 +00:00

Inputs

Revert "Revert "DI: Fold constant arguments into a single MDString""

2014-10-03 20:01:09 +00:00

Mips

[mips][microMIPS] Implement CodeGen support for SLL16 and SRL16 instructions

2014-11-05 15:46:53 +00:00

MSP430

Drop the W postfix on the 16-bit registers.

2014-09-10 06:58:14 +00:00

NVPTX

[NVPTX] aligned byte-buffers for vector return types

2014-10-25 03:46:16 +00:00

PowerPC

[PowerPC] Initial VSX intrinsic support, with min/max for vector double

2014-10-31 19:19:07 +00:00

R600

R600/SI: Change all instruction assembly names to lowercase.

2014-11-05 14:50:53 +00:00

SPARC

Add back tests for empty function in SPARC and PowerPC.

2014-09-15 22:11:07 +00:00

SystemZ

IR: add "cmpxchg weak" variant to support permitted failure.

2014-06-13 14:24:07 +00:00

Thumb

Improve logic that decides if its profitable to commute when some of the virtual registers involved have uses/defs chains connecting them to physical register. Fix up the tests that this change improves.

2014-11-05 06:43:02 +00:00

Thumb2

ARM: Fix a bug which was causing convergence failure in constant-island pass.

2014-10-17 01:31:47 +00:00

X86

[X86] Teach method 'isVectorClearMaskLegal' how to check for legal blend masks.

2014-11-05 13:04:14 +00:00

XCore

Fix a bit of confusion about .set and produce more readable assembly.

2014-10-21 01:17:30 +00:00