shylie/llvm-project

History

jinchen a62a702416

[mlir][math] Add expand patterns for acosh, asinh, atanh (#90718 )

2024-05-07 13:10:37 +05:30

..

benchmark/python

[mlir][benchmark] Fix broken benchmark script (#68841 )

2023-12-06 12:17:53 +05:30

[mlir][ods] Allow sharding of op definitions (#89423 )

2024-04-24 14:58:37 -07:00

fix formatting issues with ODS docs around assembly format directives (#91149 )

2024-05-05 19:17:16 -07:00

Switch member calls to isa/dyn_cast/cast/... to free function calls. (#89356 )

2024-04-19 15:58:27 +02:00

[mlir][math] Add expand patterns for acosh, asinh, atanh (#90718 )

2024-05-07 13:10:37 +05:30

[mlir][math] Add expand patterns for acosh, asinh, atanh (#90718 )

2024-05-07 13:10:37 +05:30

[MLIR] fix _f64ElementsAttr in ir.py (#91176 )

2024-05-06 20:08:47 +08:00

[mlir][math] Add expand patterns for acosh, asinh, atanh (#90718 )

2024-05-07 13:10:37 +05:30

[mlir][ODS][NFC] Deduplicate ref and qualified handling (#91080 )

2024-05-04 21:57:22 +02:00

[mlir-lsp] Parse outgoing request callback JSON (#90693 )

2024-05-02 09:02:13 -04:00

[emacs] Fix Emacs library formatting (#76110 )

2024-01-10 13:14:21 +01:00

.clang-format

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.clang-tidy

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CMakeLists.txt

[mlir][ods] Allow sharding of op definitions (#89423 )

2024-04-24 14:58:37 -07:00

LICENSE.TXT

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README.md

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README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.