shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Craig Topper f59307bfdc [RISCV] Teach needVSETVLIPHI to handle mask register instructions. 
This handles the case where the mask register instruction input
comes from a Phi of vsetvlis. If the VLMAX is the same as the VLMAX
required by the mask register instruction, we can avoid a vsetvli.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D113204
2021-11-15 09:57:28 -08:00
..
AArch64
[AArch64][SVE] Break false dependencies for inactive lanes of FP unary operations
2021-11-15 09:15:21 +00:00
AMDGPU
[AMDGPU][MC][GFX10] Corrected global_atomic_fcmpswap*
2021-11-15 12:51:12 +03:00
ARC
…
ARM
[ARM] implement support for TLS register based stack protector
2021-11-09 18:19:47 +01:00
AVR
[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation
2021-10-11 15:28:31 -07:00
BPF
BPF: change btf_type_tag BTF output format
2021-11-09 11:34:25 -08:00
CSKY
[CSKY] First patch to construct codegen infra and generate first add instruction
2021-11-01 10:06:56 +08:00
Generic
[AIX] XFAIL 2009-03-29-SoftFloatVectorExtract.ll because of no soft float support
2021-11-10 20:58:26 -05:00
Hexagon
[LiveIntervals] Update subranges in processTiedPairs
2021-11-11 12:24:59 +00:00
Inputs
…
Lanai
…
M68k
…
Mips
[SelectionDAG] Optimize expansion for rotates/funnel shifts
2021-11-02 11:38:25 +00:00
MIR
[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC
2021-11-07 15:06:54 +00:00
MSP430
…
NVPTX
[NVPTX] Add imm variants for surface and texture instructions
2021-11-10 19:05:03 +03:00
PowerPC
[PowerPC] guard update form prepare with non-const increment with option
2021-11-15 02:16:46 +00:00
RISCV
[RISCV] Teach needVSETVLIPHI to handle mask register instructions.
2021-11-15 09:57:28 -08:00
SPARC
[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers
2021-11-14 19:59:52 +01:00
SystemZ
[SystemZ] Improvement of emitMemMemWrapper()
2021-10-26 17:03:01 +02:00
Thumb
[TwoAddressInstructionPass] Update existing physreg live intervals
2021-11-05 21:20:30 +00:00
Thumb2
[ARM] Fix GatherScatter AddLikeOr condition
2021-11-15 09:44:41 +00:00
VE
[VE][NFC] correct bitmasking in popcnt expansion test
2021-10-25 13:55:58 +02:00
WebAssembly
[WebAssembly] Add prototype relaxed float to int trunc instructions
2021-10-28 14:01:53 -07:00
WinCFGuard
…
WinEH
…
X86
[x86] fold vector (X > -1) & Y to shift+andn (2nd try)
2021-11-15 11:09:32 -05:00
XCore
…