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llvm-project/llvm/lib/Target/RISCV
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Craig Topper 0fa5aac292 [RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli. 
If an instruction's AVL operand is a PHI node in the same block,
we may be able to peek through the PHI to find vsetvli instructions
that produce the AVL in other basic blocks. If we can prove those
vsetvli instructions have the same VTYPE and were the last vsetvli
in their respective blocks, then we don't need to insert a vsetvli
for this pseudo instruction.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D103277
2021-05-27 15:34:08 -07:00
..
AsmParser
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
Disassembler
[RISCV] Fix shared libs build
2021-02-09 06:14:25 -06:00
MCTargetDesc
[RISCV] Teach vsetvli insertion to use vsetvl x0, x0 form when we can tell that VLMAX and AVL haven't changed.
2021-05-27 10:11:38 -07:00
TargetInfo
llvmbuildectomy - replace llvm-build by plain cmake
2020-11-13 10:35:24 +01:00
CMakeLists.txt
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.h
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCV.td
[RISCV][NFC] Fix formatting
2021-04-09 14:41:09 +08:00
RISCVAsmPrinter.cpp
[RISCV][NFC] Don't need to create a new STI in RISCVAsmPrinter.
2021-05-10 09:33:23 +08:00
RISCVCallingConv.td
…
RISCVCallLowering.cpp
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVCallLowering.h
[GlobalISel] Base implementation for sret demotion.
2021-01-06 10:30:50 +05:30
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVFrameLowering.cpp
[RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().
2021-05-14 21:31:06 +08:00
RISCVFrameLowering.h
[RISCV] Fix offset computation for RVV
2021-03-29 17:03:49 +00:00
RISCVInsertVSETVLI.cpp
[RISCV] Teach VSETVLI insertion to look through PHIs to prove we don't need to insert a vsetvli.
2021-05-27 15:34:08 -07:00
RISCVInstrFormats.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Add new vector instructions in v0.10.
2021-02-03 13:28:58 +08:00
RISCVInstrInfo.cpp
[RISCV] Fix typo, use addImm instead of addReg.
2021-05-27 14:04:51 -07:00
RISCVInstrInfo.h
[RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().
2021-05-14 21:31:06 +08:00
RISCVInstrInfo.td
[RISCV] Replace AddiPair ComplexPattern with a PatLeaf. NFC
2021-05-16 12:17:52 -07:00
RISCVInstrInfoA.td
[RISCV][NFC] Add explicit type i64 to RV64 only patterns.
2021-04-09 09:37:04 +08:00
RISCVInstrInfoB.td
[RISCV] Optimize xor/or with immediate in the zbs extension
2021-05-25 14:14:09 +08:00
RISCVInstrInfoC.td
[RISCV] Rename WriteShift/ReadShift scheduler classes to WriteShiftImm/ReadShiftImm. Move variable shifts from WriteIALU/ReadIALU to new WriteShiftReg/ReadShiftReg.
2021-03-19 20:39:49 -07:00
RISCVInstrInfoD.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrInfoF.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstrInfoM.td
[RISCV] Add custom type legalization to form MULHSU when possible.
2021-04-01 10:15:55 -07:00
RISCVInstrInfoV.td
[RISCV] Temporary in vmsge(u).vx pseudo instructions can't be V0.
2021-04-21 14:50:29 -07:00
RISCVInstrInfoVPseudos.td
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Minor vector instruction tablegen cleanup. NFC
2021-05-06 11:23:59 -07:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns
2021-05-18 09:21:25 +01:00
RISCVInstrInfoZfh.td
[RISCV] Cleanup instruction formats used for B extension ternary operations.
2021-05-06 08:59:05 -07:00
RISCVInstructionSelector.cpp
…
RISCVISelDAGToDAG.cpp
[RISCV] Optimize SEW=64 shifts by splat on RV32.
2021-05-26 10:23:32 -07:00
RISCVISelDAGToDAG.h
[RISCV] Optimize SEW=64 shifts by splat on RV32.
2021-05-26 10:23:32 -07:00
RISCVISelLowering.cpp
[VP][SelectionDAG] Add a target-configurable EVL operand type
2021-05-27 15:27:36 +01:00
RISCVISelLowering.h
[VP][SelectionDAG] Add a target-configurable EVL operand type
2021-05-27 15:27:36 +01:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
[RISCV] Don't emit save-restore call if function is a interrupt handler
2021-04-16 12:54:47 +08:00
RISCVMCInstLower.cpp
[RISCV] Move instruction information into the RISCVII namespace (NFC)
2021-05-11 16:32:42 -05:00
RISCVMergeBaseOffset.cpp
[RISCV] Support Zfh half-precision floating-point extension.
2020-12-03 09:16:33 +08:00
RISCVRegisterBankInfo.cpp
…
RISCVRegisterBankInfo.h
…
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
[RISCV] Add the DebugLoc parameter to getVLENFactoredAmount().
2021-05-14 21:31:06 +08:00
RISCVRegisterInfo.h
[RISCV] Improve register allocation around vector masks
2021-02-20 14:47:51 +00:00
RISCVRegisterInfo.td
[RISCV] Introduce floating point control and state registers
2021-04-21 12:55:30 +07:00
RISCVSchedRocket.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVSchedSiFive7.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVSchedule.td
[RISCV] Add UnsupportedSchedZfh multiclass to reduce duplicate lines from RISCVSchedRocket.td and RISCVSchedSiFive7.td. NFC
2021-03-31 15:06:14 -07:00
RISCVScheduleB.td
[RISCV] Move scheduling resources for B into a separate file (NFC)
2021-03-29 20:37:22 -05:00
RISCVSubtarget.cpp
[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
2021-04-23 15:06:20 -07:00
RISCVSubtarget.h
[RISCV] Move getLMULForFixedLengthVector out of RISCVSubtarget.
2021-04-23 15:06:20 -07:00
RISCVSystemOperands.td
RISCV: add a few deprecated aliases for CSRs
2021-05-21 13:52:58 -07:00
RISCVTargetMachine.cpp
[RISCV] Add a vsetvli insert pass that can be extended to be aware of incoming VL/VTYPE from other basic blocks.
2021-05-24 11:47:27 -07:00
RISCVTargetMachine.h
[RISCV] Address clang-tidy warnings in RISCVTargetMachine. NFC.
2020-12-18 21:50:55 +00:00
RISCVTargetObjectFile.cpp
ELF: Create unique SHF_GNU_RETAIN sections for llvm.used global objects
2021-02-26 16:38:44 -08:00
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add support for fmin/fmax vector reductions
2021-05-03 10:33:51 +01:00
RISCVTargetTransformInfo.h
[RISCV] Add legality check for vectorizing reduction
2021-05-20 17:45:46 +08:00