2edcde00cb
Early revisions of the VR4300 have a hardware bug where two consecutive multiplications can produce an incorrect result in the second multiply. This revision adds the `-mfix4300` flag to llvm (and clang) which, when passed, provides a software fix for this issue. More precise description of the "mulmul" bug: ``` mul.[s,d] fd,fs,ft mul.[s,d] fd,fs,ft or [D]MULT[U] rs,rt ``` When the above sequence is executed by the CPU, if at least one of the source operands of the first mul instruction happens to be `sNaN`, `0` or `Infinity`, then the second mul instruction may produce an incorrect result. This can happen both if the two mul instructions are next to each other and if the first one is in a delay slot and the second is the first instruction of the branch target. Description of the fix: This fix adds a backend pass to llvm which scans for mul instructions in each basic block and inserts a nop whenever the following conditions are met: - The current instruction is a single or double-precision floating-point mul instruction. - The next instruction is either a mul instruction (any kind) or a branch instruction. Differential Revision: https://reviews.llvm.org/D116238
55 lines
1.9 KiB
C++
55 lines
1.9 KiB
C++
//===-- Mips.h - Top-level interface for Mips representation ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in
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// the LLVM Mips back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPS_H
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#define LLVM_LIB_TARGET_MIPS_MIPS_H
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class MipsTargetMachine;
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class ModulePass;
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class FunctionPass;
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class MipsRegisterBankInfo;
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class MipsSubtarget;
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class MipsTargetMachine;
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class InstructionSelector;
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class PassRegistry;
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ModulePass *createMipsOs16Pass();
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ModulePass *createMips16HardFloatPass();
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FunctionPass *createMipsModuleISelDagPass();
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FunctionPass *createMipsOptimizePICCallPass();
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FunctionPass *createMipsDelaySlotFillerPass();
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FunctionPass *createMipsBranchExpansion();
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FunctionPass *createMipsConstantIslandPass();
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FunctionPass *createMicroMipsSizeReducePass();
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FunctionPass *createMipsExpandPseudoPass();
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FunctionPass *createMipsPreLegalizeCombiner();
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FunctionPass *createMipsMulMulBugPass();
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InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
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MipsSubtarget &,
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MipsRegisterBankInfo &);
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void initializeMipsDelaySlotFillerPass(PassRegistry &);
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void initializeMipsBranchExpansionPass(PassRegistry &);
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void initializeMicroMipsSizeReducePass(PassRegistry &);
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void initializeMipsPreLegalizerCombinerPass(PassRegistry&);
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void initializeMipsMulMulBugFixPass(PassRegistry&);
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} // end namespace llvm;
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#endif
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