Matt Arsenault f68cc2a7ed AMDGPU: Use 128-bit DS operations by default

2020-04-02 17:17:47 -04:00

..

AArch64

Fix RUN line in AArch64/speculation-hardening.ll

2020-04-02 09:42:15 +01:00

AMDGPU

AMDGPU: Use 128-bit DS operations by default

2020-04-02 17:17:47 -04:00

ARC

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ARM

[ARM] Fix qdadd operand order

2020-03-31 10:11:36 +01:00

AVR

[AVR] Generalize the previous interrupt bugfix to signal handlers too

2020-03-31 19:33:34 +13:00

BPF

[BPF] support 128bit int explicitly in layout spec

2020-03-28 11:46:29 -07:00

Generic

[X86] Move combineLoopMAddPattern and combineLoopSADPattern to an IR pass before SelecitonDAG.

2020-03-26 14:10:20 -07:00

Hexagon

Revert "Include static prof data when collecting loop BBs"

2020-03-24 09:41:16 -07:00

Inputs

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Lanai

Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""

2020-02-13 10:16:06 -08:00

Mips

[Mips] Make MipsBranchExpansion aware of BBIT family of branch

2020-03-31 09:20:51 +02:00

MIR

AMDGPU: Assume f32 denormals are enabled by default

2020-04-02 17:17:12 -04:00

MSP430

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NVPTX

[DAGCombiner] Require ninf for sqrt recip estimation

2020-04-01 16:23:43 +08:00

PowerPC

[NFC][PowerPC] Using update_llc_test_checks.py to update atomics-regression.ll

2020-04-02 12:47:35 +00:00

RISCV

[LegalizeTypes][RISCV] Correctly sign-extend comparison for ATOMIC_CMP_XCHG

2020-04-01 15:51:26 +01:00

SPARC

[Sparc] Fix incorrect operand for matching CMPri pattern

2020-03-02 11:36:32 +08:00

SystemZ

[LoopDataPrefetch + SystemZ] Let target decide on prefetching for each loop.

2020-04-02 14:57:46 +02:00

Thumb

[DAGCombine] Skip PostInc combine with later users

2020-03-23 08:39:53 +00:00

Thumb2

[ARM] MVE VMULL patterns

2020-04-02 10:57:40 +01:00

VE

[VE] Target-specific bit size for sjljehprepare

2020-03-10 17:51:16 +01:00

WebAssembly

[WebAssembly] EmscriptenEHSjLj: Mark __invoke_ functions as imported

2020-04-01 16:33:33 -07:00

WinCFGuard

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WinEH

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X86

[X86] Enable combineExtSetcc for vectors larger than 256 bits when we've disabled 512 bit vectors.

2020-04-02 12:44:27 -07:00

XCore

[XCore] Add instruction pattern for bitrev

2020-02-21 09:28:49 +08:00