f7060f4f88
Since SRSRC has alignment requirements, first find non GIT pointer clobbered registers for SRSRC and then if those registers clobber preloaded Scratch Wave Offset register, copy the Scratch Wave Offset register to a free SGPR.
557 lines
19 KiB
C++
557 lines
19 KiB
C++
//===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "SIMachineFunctionInfo.h"
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#include "AMDGPUArgumentUsageInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "AMDGPUSubtarget.h"
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#include "SIRegisterInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/Optional.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/CallingConv.h"
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#include "llvm/IR/Function.h"
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#include <cassert>
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#include <vector>
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#define MAX_LANES 64
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using namespace llvm;
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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PrivateSegmentBuffer(false),
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DispatchPtr(false),
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QueuePtr(false),
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KernargSegmentPtr(false),
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DispatchID(false),
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FlatScratchInit(false),
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WorkGroupIDX(false),
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WorkGroupIDY(false),
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WorkGroupIDZ(false),
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WorkGroupInfo(false),
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PrivateSegmentWaveByteOffset(false),
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WorkItemIDX(false),
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WorkItemIDY(false),
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WorkItemIDZ(false),
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ImplicitBufferPtr(false),
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ImplicitArgPtr(false),
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GITPtrHigh(0xffffffff),
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HighBitsOf32BitAddress(0),
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GDSSize(0) {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const Function &F = MF.getFunction();
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FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
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WavesPerEU = ST.getWavesPerEU(F);
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Occupancy = ST.computeOccupancy(MF, getLDSSize());
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CallingConv::ID CC = F.getCallingConv();
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const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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// FIXME: Should have analysis or something rather than attribute to detect
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// calls.
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const bool HasCalls = FrameInfo.hasCalls() || F.hasFnAttribute("amdgpu-calls");
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// Enable all kernel inputs if we have the fixed ABI. Don't bother if we don't
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// have any calls.
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const bool UseFixedABI = AMDGPUTargetMachine::EnableFixedFunctionABI &&
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(!isEntryFunction() || HasCalls);
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if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
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if (!F.arg_empty())
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KernargSegmentPtr = true;
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WorkGroupIDX = true;
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WorkItemIDX = true;
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} else if (CC == CallingConv::AMDGPU_PS) {
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PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
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}
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if (!isEntryFunction()) {
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// Non-entry functions have no special inputs for now, other registers
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// required for scratch access.
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ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
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// TODO: Pick a high register, and shift down, similar to a kernel.
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FrameOffsetReg = AMDGPU::SGPR33;
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StackPtrOffsetReg = AMDGPU::SGPR32;
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ArgInfo.PrivateSegmentBuffer =
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ArgDescriptor::createRegister(ScratchRSrcReg);
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if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
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ImplicitArgPtr = true;
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} else {
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if (F.hasFnAttribute("amdgpu-implicitarg-ptr")) {
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KernargSegmentPtr = true;
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MaxKernArgAlign = std::max(ST.getAlignmentForImplicitArgPtr(),
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MaxKernArgAlign);
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}
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}
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if (UseFixedABI) {
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WorkGroupIDX = true;
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WorkGroupIDY = true;
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WorkGroupIDZ = true;
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WorkItemIDX = true;
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WorkItemIDY = true;
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WorkItemIDZ = true;
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ImplicitArgPtr = true;
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} else {
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if (F.hasFnAttribute("amdgpu-work-group-id-x"))
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WorkGroupIDX = true;
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if (F.hasFnAttribute("amdgpu-work-group-id-y"))
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WorkGroupIDY = true;
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if (F.hasFnAttribute("amdgpu-work-group-id-z"))
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WorkGroupIDZ = true;
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if (F.hasFnAttribute("amdgpu-work-item-id-x"))
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WorkItemIDX = true;
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if (F.hasFnAttribute("amdgpu-work-item-id-y"))
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WorkItemIDY = true;
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if (F.hasFnAttribute("amdgpu-work-item-id-z"))
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WorkItemIDZ = true;
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}
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bool HasStackObjects = FrameInfo.hasStackObjects();
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if (isEntryFunction()) {
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// X, XY, and XYZ are the only supported combinations, so make sure Y is
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// enabled if Z is.
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if (WorkItemIDZ)
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WorkItemIDY = true;
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PrivateSegmentWaveByteOffset = true;
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// HS and GS always have the scratch wave offset in SGPR5 on GFX9.
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if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
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(CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
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ArgInfo.PrivateSegmentWaveByteOffset =
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ArgDescriptor::createRegister(AMDGPU::SGPR5);
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}
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bool isAmdHsaOrMesa = ST.isAmdHsaOrMesa(F);
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if (isAmdHsaOrMesa) {
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PrivateSegmentBuffer = true;
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if (UseFixedABI) {
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DispatchPtr = true;
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QueuePtr = true;
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// FIXME: We don't need this?
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DispatchID = true;
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} else {
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if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
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DispatchPtr = true;
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if (F.hasFnAttribute("amdgpu-queue-ptr"))
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QueuePtr = true;
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if (F.hasFnAttribute("amdgpu-dispatch-id"))
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DispatchID = true;
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}
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} else if (ST.isMesaGfxShader(F)) {
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ImplicitBufferPtr = true;
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}
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if (UseFixedABI || F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
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KernargSegmentPtr = true;
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if (ST.hasFlatAddressSpace() && isEntryFunction() && isAmdHsaOrMesa) {
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auto hasNonSpillStackObjects = [&]() {
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// Avoid expensive checking if there's no stack objects.
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if (!HasStackObjects)
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return false;
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for (auto OI = FrameInfo.getObjectIndexBegin(),
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OE = FrameInfo.getObjectIndexEnd(); OI != OE; ++OI)
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if (!FrameInfo.isSpillSlotObjectIndex(OI))
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return true;
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// All stack objects are spill slots.
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return false;
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};
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// TODO: This could be refined a lot. The attribute is a poor way of
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// detecting calls that may require it before argument lowering.
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if (HasCalls || hasNonSpillStackObjects())
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FlatScratchInit = true;
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}
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Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
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StringRef S = A.getValueAsString();
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if (!S.empty())
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S.consumeInteger(0, GITPtrHigh);
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A = F.getFnAttribute("amdgpu-32bit-address-high-bits");
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S = A.getValueAsString();
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if (!S.empty())
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S.consumeInteger(0, HighBitsOf32BitAddress);
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S = F.getFnAttribute("amdgpu-gds-size").getValueAsString();
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if (!S.empty())
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S.consumeInteger(0, GDSSize);
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}
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void SIMachineFunctionInfo::limitOccupancy(const MachineFunction &MF) {
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limitOccupancy(getMaxWavesPerEU());
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const GCNSubtarget& ST = MF.getSubtarget<GCNSubtarget>();
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limitOccupancy(ST.getOccupancyWithLocalMemSize(getLDSSize(),
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MF.getFunction()));
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}
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Register SIMachineFunctionInfo::addPrivateSegmentBuffer(
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const SIRegisterInfo &TRI) {
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ArgInfo.PrivateSegmentBuffer =
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ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SGPR_128RegClass));
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NumUserSGPRs += 4;
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return ArgInfo.PrivateSegmentBuffer.getRegister();
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}
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Register SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
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ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.DispatchPtr.getRegister();
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}
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Register SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
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ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.QueuePtr.getRegister();
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}
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Register SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
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ArgInfo.KernargSegmentPtr
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= ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.KernargSegmentPtr.getRegister();
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}
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Register SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
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ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.DispatchID.getRegister();
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}
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Register SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
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ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.FlatScratchInit.getRegister();
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}
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Register SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
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ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
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getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
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NumUserSGPRs += 2;
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return ArgInfo.ImplicitBufferPtr.getRegister();
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}
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static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
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for (unsigned I = 0; CSRegs[I]; ++I) {
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if (CSRegs[I] == Reg)
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return true;
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}
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return false;
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}
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/// \p returns true if \p NumLanes slots are available in VGPRs already used for
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/// SGPR spilling.
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//
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// FIXME: This only works after processFunctionBeforeFrameFinalized
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bool SIMachineFunctionInfo::haveFreeLanesForSGPRSpill(const MachineFunction &MF,
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unsigned NumNeed) const {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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unsigned WaveSize = ST.getWavefrontSize();
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return NumVGPRSpillLanes + NumNeed <= WaveSize * SpillVGPRs.size();
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}
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/// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
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bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
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int FI) {
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std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
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// This has already been allocated.
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if (!SpillLanes.empty())
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return true;
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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unsigned WaveSize = ST.getWavefrontSize();
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unsigned Size = FrameInfo.getObjectSize(FI);
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assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
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assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
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int NumLanes = Size / 4;
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const MCPhysReg *CSRegs = MRI.getCalleeSavedRegs();
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// Make sure to handle the case where a wide SGPR spill may span between two
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// VGPRs.
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for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
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Register LaneVGPR;
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unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
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if (VGPRIndex == 0) {
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LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
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if (LaneVGPR == AMDGPU::NoRegister) {
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// We have no VGPRs left for spilling SGPRs. Reset because we will not
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// partially spill the SGPR to VGPRs.
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SGPRToVGPRSpills.erase(FI);
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NumVGPRSpillLanes -= I;
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return false;
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}
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Optional<int> CSRSpillFI;
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if ((FrameInfo.hasCalls() || !isEntryFunction()) && CSRegs &&
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isCalleeSavedReg(CSRegs, LaneVGPR)) {
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CSRSpillFI = FrameInfo.CreateSpillStackObject(4, Align(4));
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}
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SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
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// Add this register as live-in to all blocks to avoid machine verifer
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// complaining about use of an undefined physical register.
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for (MachineBasicBlock &BB : MF)
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BB.addLiveIn(LaneVGPR);
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} else {
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LaneVGPR = SpillVGPRs.back().VGPR;
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}
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SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
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}
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return true;
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}
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/// Reserve AGPRs or VGPRs to support spilling for FrameIndex \p FI.
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/// Either AGPR is spilled to VGPR to vice versa.
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/// Returns true if a \p FI can be eliminated completely.
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bool SIMachineFunctionInfo::allocateVGPRSpillToAGPR(MachineFunction &MF,
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int FI,
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bool isAGPRtoVGPR) {
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MachineRegisterInfo &MRI = MF.getRegInfo();
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MachineFrameInfo &FrameInfo = MF.getFrameInfo();
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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assert(ST.hasMAIInsts() && FrameInfo.isSpillSlotObjectIndex(FI));
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auto &Spill = VGPRToAGPRSpills[FI];
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// This has already been allocated.
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if (!Spill.Lanes.empty())
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return Spill.FullyAllocated;
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unsigned Size = FrameInfo.getObjectSize(FI);
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unsigned NumLanes = Size / 4;
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Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
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const TargetRegisterClass &RC =
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isAGPRtoVGPR ? AMDGPU::VGPR_32RegClass : AMDGPU::AGPR_32RegClass;
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auto Regs = RC.getRegisters();
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auto &SpillRegs = isAGPRtoVGPR ? SpillAGPR : SpillVGPR;
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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Spill.FullyAllocated = true;
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// FIXME: Move allocation logic out of MachineFunctionInfo and initialize
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// once.
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BitVector OtherUsedRegs;
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OtherUsedRegs.resize(TRI->getNumRegs());
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const uint32_t *CSRMask =
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TRI->getCallPreservedMask(MF, MF.getFunction().getCallingConv());
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if (CSRMask)
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OtherUsedRegs.setBitsInMask(CSRMask);
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// TODO: Should include register tuples, but doesn't matter with current
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// usage.
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for (MCPhysReg Reg : SpillAGPR)
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OtherUsedRegs.set(Reg);
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for (MCPhysReg Reg : SpillVGPR)
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OtherUsedRegs.set(Reg);
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SmallVectorImpl<MCPhysReg>::const_iterator NextSpillReg = Regs.begin();
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for (unsigned I = 0; I < NumLanes; ++I) {
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NextSpillReg = std::find_if(
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NextSpillReg, Regs.end(), [&MRI, &OtherUsedRegs](MCPhysReg Reg) {
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return MRI.isAllocatable(Reg) && !MRI.isPhysRegUsed(Reg) &&
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!OtherUsedRegs[Reg];
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});
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if (NextSpillReg == Regs.end()) { // Registers exhausted
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Spill.FullyAllocated = false;
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break;
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}
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OtherUsedRegs.set(*NextSpillReg);
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SpillRegs.push_back(*NextSpillReg);
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Spill.Lanes[I] = *NextSpillReg++;
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}
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return Spill.FullyAllocated;
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}
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void SIMachineFunctionInfo::removeDeadFrameIndices(MachineFrameInfo &MFI) {
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// The FP spill hasn't been inserted yet, so keep it around.
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for (auto &R : SGPRToVGPRSpills) {
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if (R.first != FramePointerSaveIndex)
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MFI.RemoveStackObject(R.first);
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}
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// All other SPGRs must be allocated on the default stack, so reset the stack
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// ID.
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for (int i = MFI.getObjectIndexBegin(), e = MFI.getObjectIndexEnd(); i != e;
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++i)
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if (i != FramePointerSaveIndex)
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MFI.setStackID(i, TargetStackID::Default);
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for (auto &R : VGPRToAGPRSpills) {
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if (R.second.FullyAllocated)
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MFI.RemoveStackObject(R.first);
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}
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}
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MCPhysReg SIMachineFunctionInfo::getNextUserSGPR() const {
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assert(NumSystemSGPRs == 0 && "System SGPRs must be added after user SGPRs");
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return AMDGPU::SGPR0 + NumUserSGPRs;
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}
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MCPhysReg SIMachineFunctionInfo::getNextSystemSGPR() const {
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return AMDGPU::SGPR0 + NumUserSGPRs + NumSystemSGPRs;
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}
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Register
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SIMachineFunctionInfo::getGITPtrLoReg(const MachineFunction &MF) const {
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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if (!ST.isAmdPalOS())
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return Register();
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Register GitPtrLo = AMDGPU::SGPR0; // Low GIT address passed in
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if (ST.hasMergedShaders()) {
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switch (MF.getFunction().getCallingConv()) {
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case CallingConv::AMDGPU_HS:
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case CallingConv::AMDGPU_GS:
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// Low GIT address is passed in s8 rather than s0 for an LS+HS or
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// ES+GS merged shader on gfx9+.
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GitPtrLo = AMDGPU::SGPR8;
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return GitPtrLo;
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default:
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return GitPtrLo;
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}
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}
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return GitPtrLo;
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}
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static yaml::StringValue regToString(Register Reg,
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const TargetRegisterInfo &TRI) {
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yaml::StringValue Dest;
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{
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raw_string_ostream OS(Dest.Value);
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OS << printReg(Reg, &TRI);
|
|
}
|
|
return Dest;
|
|
}
|
|
|
|
static Optional<yaml::SIArgumentInfo>
|
|
convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo,
|
|
const TargetRegisterInfo &TRI) {
|
|
yaml::SIArgumentInfo AI;
|
|
|
|
auto convertArg = [&](Optional<yaml::SIArgument> &A,
|
|
const ArgDescriptor &Arg) {
|
|
if (!Arg)
|
|
return false;
|
|
|
|
// Create a register or stack argument.
|
|
yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister());
|
|
if (Arg.isRegister()) {
|
|
raw_string_ostream OS(SA.RegisterName.Value);
|
|
OS << printReg(Arg.getRegister(), &TRI);
|
|
} else
|
|
SA.StackOffset = Arg.getStackOffset();
|
|
// Check and update the optional mask.
|
|
if (Arg.isMasked())
|
|
SA.Mask = Arg.getMask();
|
|
|
|
A = SA;
|
|
return true;
|
|
};
|
|
|
|
bool Any = false;
|
|
Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer);
|
|
Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr);
|
|
Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr);
|
|
Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr);
|
|
Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID);
|
|
Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit);
|
|
Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize);
|
|
Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX);
|
|
Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY);
|
|
Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ);
|
|
Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo);
|
|
Any |= convertArg(AI.PrivateSegmentWaveByteOffset,
|
|
ArgInfo.PrivateSegmentWaveByteOffset);
|
|
Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr);
|
|
Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr);
|
|
Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX);
|
|
Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY);
|
|
Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ);
|
|
|
|
if (Any)
|
|
return AI;
|
|
|
|
return None;
|
|
}
|
|
|
|
yaml::SIMachineFunctionInfo::SIMachineFunctionInfo(
|
|
const llvm::SIMachineFunctionInfo& MFI,
|
|
const TargetRegisterInfo &TRI)
|
|
: ExplicitKernArgSize(MFI.getExplicitKernArgSize()),
|
|
MaxKernArgAlign(MFI.getMaxKernArgAlign()),
|
|
LDSSize(MFI.getLDSSize()),
|
|
IsEntryFunction(MFI.isEntryFunction()),
|
|
NoSignedZerosFPMath(MFI.hasNoSignedZerosFPMath()),
|
|
MemoryBound(MFI.isMemoryBound()),
|
|
WaveLimiter(MFI.needsWaveLimiter()),
|
|
HighBitsOf32BitAddress(MFI.get32BitAddressHighBits()),
|
|
ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)),
|
|
FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)),
|
|
StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)),
|
|
ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)),
|
|
Mode(MFI.getMode()) {}
|
|
|
|
void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) {
|
|
MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this);
|
|
}
|
|
|
|
bool SIMachineFunctionInfo::initializeBaseYamlFields(
|
|
const yaml::SIMachineFunctionInfo &YamlMFI) {
|
|
ExplicitKernArgSize = YamlMFI.ExplicitKernArgSize;
|
|
MaxKernArgAlign = assumeAligned(YamlMFI.MaxKernArgAlign);
|
|
LDSSize = YamlMFI.LDSSize;
|
|
HighBitsOf32BitAddress = YamlMFI.HighBitsOf32BitAddress;
|
|
IsEntryFunction = YamlMFI.IsEntryFunction;
|
|
NoSignedZerosFPMath = YamlMFI.NoSignedZerosFPMath;
|
|
MemoryBound = YamlMFI.MemoryBound;
|
|
WaveLimiter = YamlMFI.WaveLimiter;
|
|
return false;
|
|
}
|