Brandon Wu 7e6bad112c

[RISCV] Rename vcix_state register to sf_vcix_state. NFC (#106995) ...

Since it's SiFive VCIX specific register, it's better to have a prefix
so that it's more understandable.

2024-09-03 15:55:39 +08:00

..

AsmParser

[RISCV] Use MCRegister instead of unsigned in RISCVAsmParser.cpp. NFC

2024-08-31 01:02:50 -07:00

Disassembler

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

GISel

Revert "[RISCV] RISCV vector calling convention (2/2)" (#97994)

2024-08-31 19:02:35 +08:00

MCA

[RISCV][NFC] Include RISCVVInversePseudosTable in RISCVMCTargetDesc

2024-04-24 09:29:20 -07:00

MCTargetDesc

[RISCV][LoongArch] Don't store Dwarf register in MCRegister.

2024-08-30 19:32:21 -07:00

TargetInfo

…

CMakeLists.txt

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCV.h

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCV.td

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)

2024-08-14 11:42:31 +03:00

RISCVAsmPrinter.cpp

[RISCV] Mark symbols used in inline asm for relocations as referenced (#104925)

2024-08-26 15:11:24 +03:00

RISCVCallingConv.td

[RISCV] RISCV vector calling convention (1/2) (#77560)

2024-03-27 23:03:13 +08:00

RISCVCodeGenPrepare.cpp

[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329)

2024-08-01 09:37:42 +08:00

RISCVCombine.td

…

RISCVDeadRegisterDefinitions.cpp

[CodeGen][NewPM] Port LiveIntervals to new pass manager (#98118)

2024-07-10 19:34:48 +08:00

RISCVExpandAtomicPseudoInsts.cpp

…

RISCVExpandPseudoInsts.cpp

[RISCV] Fix more boundary cases in immediate selection for Zdinx load/store on RV32. (#105874)

2024-08-25 14:27:08 -07:00

RISCVFeatures.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVFrameLowering.cpp

[RISCV][CFI] Emit cfi_offset for every callee-saved vector registers (#100455)

2024-07-29 11:03:07 +08:00

RISCVFrameLowering.h

[RISCV] Add CFI information for vector callee-saved registers (#86811)

2024-04-17 10:42:40 +08:00

RISCVGatherScatterLowering.cpp

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

RISCVGISel.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVIndirectBranchTracking.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCVInsertReadWriteCSR.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVInsertVSETVLI.cpp

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVInsertWriteVXRM.cpp

[CodeGen] Make the parameter TRI required in some functions. (#85968)

2024-04-24 14:24:14 +01:00

RISCVInstrFormats.td

[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517)

2024-08-30 07:46:06 +08:00

RISCVInstrFormatsC.td

…

RISCVInstrFormatsV.td

…

RISCVInstrGISel.td

[RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_ICMP for scalable vector types

2024-04-03 15:27:15 -07:00

RISCVInstrInfo.cpp

[MachineOutliner][NFC] Refactor (#105398)

2024-08-27 14:38:36 -07:00

RISCVInstrInfo.h

[MachineOutliner][NFC] Refactor (#105398)

2024-08-27 14:38:36 -07:00

RISCVInstrInfo.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVInstrInfoA.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoC.td

[RISCV] Fix InsnCI register type (#100113)

2024-07-23 21:19:57 +08:00

RISCVInstrInfoD.td

[RISCV] Fix more boundary cases in immediate selection for Zdinx load/store on RV32. (#105874)

2024-08-25 14:27:08 -07:00

RISCVInstrInfoF.td

[RISCV] Correct the rounding mode for llvm.lround.i64.f32 with RV64+Zfinx.

2024-09-01 13:26:38 -07:00

RISCVInstrInfoM.td

[RISCV][GISel] Move i32 patterns that aren't used by SelectionDAG to RISCVGISel.td. NFC (#102685)

2024-08-12 09:34:02 -07:00

RISCVInstrInfoSFB.td

[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945)

2024-02-07 16:03:30 +08:00

RISCVInstrInfoV.td

[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517)

2024-08-30 07:46:06 +08:00

RISCVInstrInfoVPseudos.td

[RISCV] Use getAllOnesConstant/getSignedConstant.

2024-08-17 00:18:41 -07:00

RISCVInstrInfoVSDPatterns.td

[RISCV] Remove RISCVISD::FP_EXTEND_BF16. (#106939)

2024-09-02 10:14:04 -07:00

RISCVInstrInfoVVLPatterns.td

[RISCV] Add back missing vmv_v_x_vl pattern predicates (#101455)

2024-08-01 15:25:36 +08:00

RISCVInstrInfoXCV.td

[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)

2024-07-15 10:25:25 +10:00

RISCVInstrInfoXSf.td

[RISCV] Rename vcix_state register to sf_vcix_state. NFC (#106995)

2024-09-03 15:55:39 +08:00

RISCVInstrInfoXTHead.td

[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517)

2024-08-30 07:46:06 +08:00

RISCVInstrInfoXVentana.td

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

2024-07-27 17:26:32 -07:00

RISCVInstrInfoXwch.td

[RISCV] Add QingKe "XW" compressed opcode extension (#97925)

2024-07-11 11:10:02 +08:00

RISCVInstrInfoZa.td

DAG: Replace bitwidth with type in suffix in atomic tablegen ops (#94845)

2024-06-13 11:52:22 +02:00

RISCVInstrInfoZalasr.td

[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)

2024-02-01 10:58:21 -08:00

RISCVInstrInfoZb.td

[RISCV] Improve BCLRITwoBitsMaskHigh SDNodeXForm. NFC

2024-08-19 10:32:47 -07:00

RISCVInstrInfoZc.td

[RISCV] Make M imply Zmmul (#95070)

2024-06-21 11:11:10 +08:00

RISCVInstrInfoZcmop.td

[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)

2024-04-15 22:33:14 -07:00

RISCVInstrInfoZfa.td

…

RISCVInstrInfoZfbfmin.td

[RISCV] Correct the scheduler class for FCVT_S_BF16. (#107028)

2024-09-02 18:36:01 -07:00

RISCVInstrInfoZfh.td

[RISCV] Custom promote f16 (l)lround/(l)lrint with Zfhmin/Zhinxmin instead of using isel patterns.

2024-09-01 13:44:52 -07:00

RISCVInstrInfoZicbo.td

…

RISCVInstrInfoZicfiss.td

[RISCV] Add MC layer support for Zicfiss. (#66043)

2023-12-30 15:40:20 +08:00

RISCVInstrInfoZicond.td

[RISCV] Graduate Zicond to non-experimental (#79811)

2024-01-29 15:58:54 +00:00

RISCVInstrInfoZimop.td

[RISCV] Zimop/Zcmop are ratified

2024-04-08 16:40:02 +08:00

RISCVInstrInfoZk.td

…

RISCVInstrInfoZvfbf.td

…

RISCVInstrInfoZvk.td

[RISCV] Separate ActiveElementsAffectResult into VL and Mask flags (#106517)

2024-08-30 07:46:06 +08:00

RISCVISelDAGToDAG.cpp

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

RISCVISelDAGToDAG.h

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

RISCVISelLowering.cpp

[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)

2024-09-02 22:04:09 -07:00

RISCVISelLowering.h

[RISCV] Remove RISCVISD::FP_EXTEND_BF16. (#106939)

2024-09-02 10:14:04 -07:00

RISCVLandingPadSetup.cpp

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

RISCVMachineFunctionInfo.cpp

…

RISCVMachineFunctionInfo.h

[llvm-project] Fix typo "seperate" (#95373)

2024-06-13 20:20:27 +01:00

RISCVMacroFusion.td

[RISCV] Use TableGen-based macro fusion (#72224)

2024-01-25 17:10:49 +08:00

RISCVMakeCompressible.cpp

[RISCV] Teach RISCVMakeCompressible handle byte/half load/store for Zcb. (#83375)

2024-03-27 13:40:38 +08:00

RISCVMergeBaseOffset.cpp

[RISCV] Don't crash in RISCVMergeBaseOffset if INLINE_ASM uses address register in a non-memory constraint. (#100790)

2024-07-26 17:11:01 -07:00

RISCVMoveMerger.cpp

…

RISCVOptWInstrs.cpp

[RISCV] Add some Zfinx instructions to hasAllNBitUsers.

2024-08-08 17:33:54 -07:00

RISCVPostRAExpandPseudoInsts.cpp

[RISCV] Remove unneeded code from RISCVPostRAExpandPseudo::expandMovImm. NFC

2024-06-27 18:42:27 -07:00

RISCVProcessors.td

[RISCV] Add Hazard3 Core as taped out for RP2350 (#102452)

2024-08-21 08:45:45 +01:00

RISCVProfiles.td

[RISCV] Use listconcat to shorten some of the profile feature lists. (#102356)

2024-08-08 09:15:43 -07:00

RISCVPushPopOptimizer.cpp

[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)

2024-02-07 14:30:45 -08:00

RISCVRedundantCopyElimination.cpp

[RISCV] Codegen support for XCVbi extension (#89719)

2024-05-08 11:22:16 +08:00

RISCVRegisterInfo.cpp

[RISCV] Rename vcix_state register to sf_vcix_state. NFC (#106995)

2024-09-03 15:55:39 +08:00

RISCVRegisterInfo.h

[RISCV] Store VLMul/NF into RegisterClass's TSFlags

2024-04-08 13:35:37 +08:00

RISCVRegisterInfo.td

[RISCV] Rename vcix_state register to sf_vcix_state. NFC (#106995)

2024-09-03 15:55:39 +08:00

RISCVSchedRocket.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSchedSiFive7.td

[RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (#106671)

2024-09-01 21:02:06 -07:00

RISCVSchedSiFiveP400.td

[RISCV] Add vector and vector crypto to SiFiveP400 scheduler model (#102155)

2024-08-19 09:41:42 -04:00

RISCVSchedSiFiveP600.td

[RISCV] Rename merge operand -> passthru. NFC (#100330)

2024-07-30 17:47:00 +08:00

RISCVSchedSyntacoreSCR1.td

[RISCV][NFC] Cleanup SCR1 sched model (#96088)

2024-06-20 18:14:09 +03:00

RISCVSchedSyntacoreSCR345.td

[RISCV] Add scheduling model for Syntacore SCR4 and SCR5 (#102909)

2024-08-14 11:42:31 +03:00

RISCVSchedule.td

[RISCV][NFC] Add UnsupportedSched<F|D|A> multiclasses (#95948)

2024-06-19 12:37:47 +03:00

RISCVScheduleV.td

[RISCV] Move VLDSX0Pred from RISCVSchedSiFive7.td to RISCVScheduleV.td. NFC (#106671)

2024-09-01 21:02:06 -07:00

RISCVScheduleXSf.td

[RISCV] Add scheduling information for SiFive VCIX (#86093)

2024-04-16 13:55:45 +08:00

RISCVScheduleZb.td

[RISCV] Add sched classes for Zbb integer min max instructions

2024-03-14 06:02:42 -07:00

RISCVScheduleZvk.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSchedXiangShanNanHu.td

[RISCV] Add Sched classes for vector crypto instructions (#90068)

2024-05-03 11:11:29 -04:00

RISCVSubtarget.cpp

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00

RISCVSubtarget.h

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)

2024-08-01 12:24:25 +08:00

RISCVSystemOperands.td

[RISCV] Add CSRs and an instruction for Smctr and Ssctr extensions. (#105148)

2024-08-21 19:23:07 -07:00

RISCVTargetMachine.cpp

[LSR] Split the -lsr-term-fold transformation into it's own pass (#104234)

2024-08-17 18:34:23 -07:00

RISCVTargetMachine.h

[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082)

2024-07-02 18:48:28 -07:00

RISCVTargetObjectFile.cpp

[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)

2024-08-23 14:06:12 +01:00

RISCVTargetObjectFile.h

[Driver] Default -msmall-data-limit= to 0 and clean up code

2024-08-19 18:20:02 -07:00

RISCVTargetTransformInfo.cpp

[RISCV][TTI] Scale the cost of FP-Int conversion with LMUL (#87506)

2024-09-02 09:38:42 +08:00

RISCVTargetTransformInfo.h

[RISCV][TTI] Add legality check of vector of address for gather/scatter. (#106481)

2024-08-30 10:50:15 +08:00

RISCVVectorPeephole.cpp

[RISCV] Discard the false operand in vmerge.vvm -> vmv.v.v peephole (#106688)

2024-08-31 13:20:53 +08:00