017f2bc181
In practice when legalizeOperands is called on a PHI node, the result is never an SGPR class and the operands are never subregs. Simplify the code accordingly by using the result regclass for all the inputs. This includes using an AV class where previously we picked either an AGPR or VGPR class.
130 lines
5.5 KiB
LLVM
130 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -march=amdgcn -mcpu=gfx950 < %s | FileCheck %s -check-prefix=GFX950
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declare hidden i32 @_ZN25__hip_builtin_threadIdx_t7__get_xEv()
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; Before #177352 this test showed poor scheduling due to register pressure
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; problems. The symptom was that two global_load instructions were immediately
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; followed by s_waitcnt vmcnt(0).
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define amdgpu_kernel void @main(i1 %arg, ptr %ptr, ptr addrspace(1) %ptr1, ptr addrspace(5) %ptr5) {
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; GFX950-LABEL: main:
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; GFX950: ; %bb.0: ; %bb
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; GFX950-NEXT: s_load_dword s33, s[4:5], 0x3c
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; GFX950-NEXT: s_mov_b32 s14, s10
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; GFX950-NEXT: s_mov_b64 s[10:11], s[6:7]
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; GFX950-NEXT: s_load_dword s6, s[4:5], 0x24
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; GFX950-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x2c
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; GFX950-NEXT: s_mov_b32 s12, s8
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; GFX950-NEXT: s_waitcnt lgkmcnt(0)
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; GFX950-NEXT: scratch_load_dwordx4 v[40:43], off, s33
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; GFX950-NEXT: s_mov_b32 s13, s9
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; GFX950-NEXT: s_bitcmp1_b32 s6, 0
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; GFX950-NEXT: s_cselect_b64 s[34:35], -1, 0
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; GFX950-NEXT: s_add_u32 s8, s4, 64
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; GFX950-NEXT: s_addc_u32 s9, s5, 0
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; GFX950-NEXT: s_getpc_b64 s[16:17]
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; GFX950-NEXT: s_add_u32 s16, s16, _ZN25__hip_builtin_threadIdx_t7__get_xEv@rel32@lo+4
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; GFX950-NEXT: s_addc_u32 s17, s17, _ZN25__hip_builtin_threadIdx_t7__get_xEv@rel32@hi+12
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; GFX950-NEXT: s_mov_b64 s[4:5], s[0:1]
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; GFX950-NEXT: s_mov_b64 s[6:7], s[2:3]
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; GFX950-NEXT: v_mov_b32_e32 v31, v0
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; GFX950-NEXT: s_mov_b32 s32, 0
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; GFX950-NEXT: s_swappc_b64 s[30:31], s[16:17]
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; GFX950-NEXT: v_mov_b32_e32 v1, 0
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; GFX950-NEXT: v_lshl_add_u64 v[10:11], v[0:1], 3, s[38:39]
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; GFX950-NEXT: global_load_dwordx4 v[2:5], v[10:11], off
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; GFX950-NEXT: global_load_dwordx4 v[6:9], v1, s[38:39]
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; GFX950-NEXT: v_mov_b32_e32 v0, 0
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; GFX950-NEXT: v_mov_b64_e32 v[10:11], s[36:37]
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; GFX950-NEXT: s_and_b64 vcc, exec, s[34:35]
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; GFX950-NEXT: v_mov_b32_e32 v12, v1
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; GFX950-NEXT: v_mov_b32_e32 v14, v1
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; GFX950-NEXT: v_mov_b32_e32 v15, v1
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; GFX950-NEXT: v_mov_b32_e32 v16, v1
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; GFX950-NEXT: v_mov_b32_e32 v18, v1
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; GFX950-NEXT: v_mov_b32_e32 v17, v1
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; GFX950-NEXT: v_mov_b32_e32 v19, v1
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; GFX950-NEXT: v_mov_b32_e32 v20, v1
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; GFX950-NEXT: v_mov_b32_e32 v21, v1
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; GFX950-NEXT: .LBB0_1: ; %bb4
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; GFX950-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX950-NEXT: v_mov_b32_e32 v13, v1
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; GFX950-NEXT: v_lshlrev_b64 v[22:23], 3, v[12:13]
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; GFX950-NEXT: v_lshl_add_u64 v[22:23], s[38:39], 0, v[22:23]
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; GFX950-NEXT: global_load_dwordx4 v[22:25], v[22:23], off
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; GFX950-NEXT: s_waitcnt lgkmcnt(0)
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; GFX950-NEXT: v_lshl_add_u64 v[26:27], v[0:1], 3, s[38:39]
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; GFX950-NEXT: s_waitcnt vmcnt(1)
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; GFX950-NEXT: v_or_b32_e32 v0, v40, v6
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; GFX950-NEXT: v_or_b32_e32 v13, v41, v7
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; GFX950-NEXT: v_or_b32_e32 v30, v42, v8
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; GFX950-NEXT: v_or_b32_e32 v31, v43, v9
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; GFX950-NEXT: global_load_dwordx4 v[26:29], v[26:27], off
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; GFX950-NEXT: v_or_b32_e32 v18, v5, v18
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; GFX950-NEXT: v_or_b32_e32 v16, v4, v16
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; GFX950-NEXT: v_or_b32_e32 v15, v3, v15
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; GFX950-NEXT: v_or_b32_e32 v14, v2, v14
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; GFX950-NEXT: v_or_b32_e32 v12, 1, v12
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; GFX950-NEXT: v_mov_b32_e32 v40, 0
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; GFX950-NEXT: v_mov_b32_e32 v41, 0
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; GFX950-NEXT: v_mov_b32_e32 v42, 0
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; GFX950-NEXT: v_mov_b32_e32 v43, 0
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; GFX950-NEXT: s_waitcnt vmcnt(1)
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; GFX950-NEXT: v_or_b32_e32 v25, v25, v31
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; GFX950-NEXT: v_or_b32_e32 v24, v24, v30
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; GFX950-NEXT: v_or_b32_e32 v23, v23, v13
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; GFX950-NEXT: v_or_b32_e32 v22, v22, v0
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; GFX950-NEXT: scratch_store_dwordx4 off, v[22:25], s33
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; GFX950-NEXT: flat_load_dword v0, v[10:11]
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; GFX950-NEXT: s_waitcnt vmcnt(0)
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; GFX950-NEXT: v_or_b32_e32 v21, v29, v21
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; GFX950-NEXT: v_or_b32_e32 v20, v28, v20
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; GFX950-NEXT: v_or_b32_e32 v19, v27, v19
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; GFX950-NEXT: v_or_b32_e32 v17, v26, v17
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; GFX950-NEXT: s_mov_b64 vcc, vcc
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; GFX950-NEXT: s_cbranch_vccz .LBB0_1
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; GFX950-NEXT: ; %bb.2: ; %bb2
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; GFX950-NEXT: v_or_b32_e32 v3, v21, v18
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; GFX950-NEXT: v_or_b32_e32 v2, v20, v16
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; GFX950-NEXT: v_or_b32_e32 v1, v19, v15
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; GFX950-NEXT: s_waitcnt lgkmcnt(0)
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; GFX950-NEXT: v_or_b32_e32 v0, v17, v14
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; GFX950-NEXT: scratch_store_dwordx4 off, v[0:3], s33
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; GFX950-NEXT: s_endpgm
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bb:
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%i = load <4 x i32>, ptr addrspace(5) %ptr5
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%i1 = tail call i32 @_ZN25__hip_builtin_threadIdx_t7__get_xEv()
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br label %bb4
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bb2: ; preds = %bb4
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%i3 = or <4 x i32> %i17, %i13
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store <4 x i32> %i3, ptr addrspace(5) %ptr5
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ret void
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bb4: ; preds = %bb4, %bb
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%i5 = phi <4 x i32> [ %i, %bb ], [ zeroinitializer, %bb4 ]
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%i6 = phi i32 [ 0, %bb ], [ %i24, %bb4 ]
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%i7 = phi i32 [ 0, %bb ], [ %i25, %bb4 ]
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%i8 = phi <4 x i32> [ zeroinitializer, %bb ], [ %i17, %bb4 ]
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%i9 = phi <4 x i32> [ zeroinitializer, %bb ], [ %i13, %bb4 ]
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%i10 = zext i32 %i1 to i64
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%i11 = getelementptr i64, ptr addrspace(1) %ptr1, i64 %i10
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%i12 = load <4 x i32>, ptr addrspace(1) %i11
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%i13 = or <4 x i32> %i12, %i9
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%i14 = zext i32 %i6 to i64
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%i15 = getelementptr i64, ptr addrspace(1) %ptr1, i64 %i14
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%i16 = load <4 x i32>, ptr addrspace(1) %i15
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%i17 = or <4 x i32> %i16, %i8
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%i18 = zext i32 %i7 to i64
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%i19 = getelementptr i64, ptr addrspace(1) %ptr1, i64 %i18
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%i20 = load <4 x i32>, ptr addrspace(1) %i19
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%i21 = load <4 x i32>, ptr addrspace(1) %ptr1
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%i22 = or <4 x i32> %i5, %i21
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%i23 = or <4 x i32> %i20, %i22
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store <4 x i32> %i23, ptr addrspace(5) %ptr5
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%i24 = load i32, ptr %ptr
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%i25 = or i32 %i7, 1
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br i1 %arg, label %bb2, label %bb4
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}
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