85 lines
2.0 KiB
LLVM
85 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s
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define i64 @f1(i64 %a, i64 %b) {
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; CHECK-LABEL: f1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbc r1, r1, r3
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; CHECK-NEXT: bx lr
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entry:
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%tmp = sub i64 %a, %b
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ret i64 %tmp
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}
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define i64 @f2(i64 %a, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsl r1, r1, #1
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; CHECK-NEXT: orr r1, r1, r0, lsr #31
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; CHECK-NEXT: rsbs r0, r2, r0, lsl #1
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; CHECK-NEXT: sbc r1, r1, r3
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; CHECK-NEXT: bx lr
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entry:
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%tmp1 = shl i64 %a, 1
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%tmp2 = sub i64 %tmp1, %b
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ret i64 %tmp2
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}
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; add with live carry
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define i64 @f3(i32 %al, i32 %bl) {
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; CHECK-LABEL: f3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: adds r0, r0, r1
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: adcs r0, r1, #0
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; CHECK-NEXT: adc r1, r2, #0
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; CHECK-NEXT: bx lr
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entry:
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; unsigned wide add
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%aw = zext i32 %al to i64
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%bw = zext i32 %bl to i64
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%cw = add i64 %aw, %bw
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; ch == carry bit
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%ch = lshr i64 %cw, 32
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%dw = add i64 %ch, %bw
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ret i64 %dw
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}
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; rdar://10073745
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define i64 @f4(i64 %x) nounwind readnone {
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; CHECK-LABEL: f4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: rsbs r0, r0, #0
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; CHECK-NEXT: rsc r1, r1, #0
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; CHECK-NEXT: bx lr
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entry:
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%0 = sub nsw i64 0, %x
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ret i64 %0
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}
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; rdar://12559385
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define i64 @f5(i32 %vi) {
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; CHECK-LABEL: f5:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movw r1, #19493
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; CHECK-NEXT: movw r2, #29433
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; CHECK-NEXT: movt r1, #57191
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; CHECK-NEXT: eor r0, r0, r1
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; CHECK-NEXT: movw r3, #46043
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; CHECK-NEXT: movt r2, #65535
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; CHECK-NEXT: adds r0, r0, r0
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; CHECK-NEXT: movw r1, #36102
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; CHECK-NEXT: sbc r2, r2, r1
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; CHECK-NEXT: movt r3, #8344
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; CHECK-NEXT: adds r0, r0, r3
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; CHECK-NEXT: adc r1, r2, r1
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; CHECK-NEXT: bx lr
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entry:
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%v0 = zext i32 %vi to i64
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%v1 = xor i64 %v0, -155057456198619
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%v4 = add i64 %v1, 155057456198619
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%v5 = add i64 %v4, %v1
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ret i64 %v5
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}
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