9811226967
This allows removing a special case hack in ARM. ARM's implementation of getExtractSubregLikeInputs has the strange property that it reports a register with a class that does not support the reported subregister index. We can however reconstrain the register to support this usage. This is an alternative to #159600. I've included the test, but the output is different. In this case version the VMOVSR is replaced with an ordinary subregister extract copy.
56 lines
2.1 KiB
LLVM
56 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s | FileCheck %s
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; Make sure there's no assertion from peephole-opt introducing illegal
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; subregister index uses.
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target triple = "thumbv7-unknown-linux-android29"
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define void @_ZN11VersionEdit10DecodeFromEv(i1 %call4, ptr %__profc__ZN11VersionEdit10DecodeFromEv) nounwind {
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; CHECK-LABEL: _ZN11VersionEdit10DecodeFromEv:
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; CHECK: @ %bb.0: @ %land.rhs.lr.ph
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; CHECK-NEXT: lsls r0, r0, #31
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; CHECK-NEXT: beq .LBB0_2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: adr r0, .LCPI0_0
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; CHECK-NEXT: vld1.64 {d0, d1}, [r0:128]
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .LBB0_2: @ %select.false
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; CHECK-NEXT: vmov.i32 q0, #0x0
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; CHECK-NEXT: .LBB0_3: @ %select.end
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; CHECK-NEXT: vldr s5, .LCPI0_1
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; CHECK-NEXT: vldr s4, .LCPI0_2
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; CHECK-NEXT: vmov.f32 s6, s0
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; CHECK-NEXT: vmov.f32 s7, s1
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; CHECK-NEXT: vst1.64 {d2, d3}, [r1]
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 4
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; CHECK-NEXT: @ %bb.4:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .long 1 @ 0x1
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; CHECK-NEXT: .long 0 @ 0x0
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; CHECK-NEXT: .LCPI0_1:
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; CHECK-NEXT: .long 0x00000000 @ float 0
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; CHECK-NEXT: .LCPI0_2:
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; CHECK-NEXT: .long 0x00000001 @ float 1.40129846E-45
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land.rhs.lr.ph:
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br i1 %call4, label %sw.bb, label %while.cond.while.end_crit_edge.split.loop.exit43
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while.cond.while.end_crit_edge.split.loop.exit43: ; preds = %land.rhs.lr.ph
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%ext0 = extractelement <4 x i64> zeroinitializer, i64 0
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br label %while.cond.while.end_crit_edge
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while.cond.while.end_crit_edge: ; preds = %sw.bb, %while.cond.while.end_crit_edge.split.loop.exit43
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%pgocount5374.ph = phi i64 [ %ext1, %sw.bb ], [ %ext0, %while.cond.while.end_crit_edge.split.loop.exit43 ]
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%ins = insertelement <2 x i64> splat (i64 1), i64 %pgocount5374.ph, i64 1
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store <2 x i64> %ins, ptr %__profc__ZN11VersionEdit10DecodeFromEv, align 8
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ret void
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sw.bb: ; preds = %land.rhs.lr.ph
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%ext1 = extractelement <4 x i64> splat (i64 1), i64 0
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br label %while.cond.while.end_crit_edge
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}
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