6117bdd903
This PR fixes a big-endian regression in `ForwardStoreValueToDirectLoad` where the wrong subvector was being extracted. In big-endian, memory offset 0 corresponds to the high bits, so the extraction index needs to be adjusted. As suggested by @KennethHilmersson, calculate the extraction index as the difference between the number of elements in the intermediate vector and the load vector when in big-endian mode. Special thanks to Kenneth Hilmersson for providing the fix logic and the ARM regression test. https://github.com/llvm/llvm-project/pull/172523#issuecomment-3878065191 https://github.com/llvm/llvm-project/pull/172523#issuecomment-3879575092
29 lines
949 B
LLVM
29 lines
949 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armeb-eabi -mattr=+v7,+neon | FileCheck %s --check-prefix=BE
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v7,+neon | FileCheck %s --check-prefix=LE
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define <2 x i32> @test_offset_load(ptr %p, <4 x i32> %v) {
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; BE-LABEL: test_offset_load:
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; BE: @ %bb.0:
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; BE-NEXT: vldr d17, [sp]
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; BE-NEXT: vmov r1, r12, d17
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; BE-NEXT: vmov d16, r3, r2
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; BE-NEXT: vst1.64 {d16, d17}, [r0:128]
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; BE-NEXT: mov r0, r12
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; BE-NEXT: bx lr
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;
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; LE-LABEL: test_offset_load:
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; LE: @ %bb.0:
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; LE-NEXT: vldr d17, [sp]
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; LE-NEXT: mov r1, #8
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; LE-NEXT: vmov d16, r2, r3
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; LE-NEXT: vst1.32 {d16, d17}, [r0:128], r1
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; LE-NEXT: vldr d16, [r0]
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; LE-NEXT: vmov r0, r1, d16
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; LE-NEXT: bx lr
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store <4 x i32> %v, ptr %p, align 16
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%p2 = getelementptr i8, ptr %p, i64 8
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%res = load <2 x i32>, ptr %p2, align 8
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ret <2 x i32> %res
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}
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