c63d2953a0
On platforms that soft promote `half`, using `lrint` intrinsics crashes
with the following:
SoftPromoteHalfOperand Op #0: t5: i32 = lrint t4
LLVM ERROR: Do not know how to soft promote this operator's operand!
PLEASE submit a bug report to
https://github.com/llvm/llvm-project/issues/ and include the crash
backtrace.
Stack dump:
0. Program arguments:
/Users/tmgross/Documents/projects/llvm/llvm-build/bin/llc
-mtriple=riscv32
1. Running pass 'Function Pass Manager' on module '<stdin>'.
2. Running pass 'RISC-V DAG->DAG Pattern Instruction Selection' on
function '@test_lrint_ixx_f16'
Resolve this by adding a soft promotion. GISel is included since tests
cover both.
Fixes crash tests added in
https://github.com/llvm/llvm-project/pull/152662 for targets that use
`softPromoteHalfType`.
Co-authored-by: Folkert de Vries <folkert@folkertdev.nl>
75 lines
1.7 KiB
LLVM
75 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=mips64el -mattr=+soft-float | FileCheck %s
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; RUN: llc < %s -mtriple=mips -mattr=+soft-float | FileCheck %s
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define signext i32 @testmswh(half %x) {
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; CHECK-LABEL: testmswh:
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; CHECK: jal llrintf
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxh(half %x) {
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; CHECK-LABEL: testmsxh:
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; CHECK: jal llrintf
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f16(half %x)
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ret i64 %0
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}
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define signext i32 @testmsws(float %x) {
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; CHECK-LABEL: testmsws:
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; CHECK: jal llrintf
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f32(float %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxs(float %x) {
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; CHECK-LABEL: testmsxs:
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; CHECK: jal llrintf
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f32(float %x)
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ret i64 %0
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}
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define signext i32 @testmswd(double %x) {
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; CHECK-LABEL: testmswd:
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; CHECK: jal llrint
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f64(double %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxd(double %x) {
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; CHECK-LABEL: testmsxd:
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; CHECK: jal llrint
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f64(double %x)
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ret i64 %0
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}
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define signext i32 @testmswl(fp128 %x) {
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; CHECK-LABEL: testmswl:
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; CHECK: jal llrintl
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f128(fp128 %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsll(fp128 %x) {
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; CHECK-LABEL: testmsll:
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; CHECK: jal llrintl
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entry:
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%0 = tail call i64 @llvm.llrint.i64.f128(fp128 %x)
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ret i64 %0
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}
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declare i64 @llvm.llrint.i64.f32(float) nounwind readnone
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declare i64 @llvm.llrint.i64.f64(double) nounwind readnone
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declare i64 @llvm.llrint.i64.f128(fp128) nounwind readnone
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