shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/PowerPC/builtins-bcd-format-conversion.ll
Aditi Medhane 7cf30a7d3d
[PowerPC] Add Support for BCDSHIFT, BCDSHIFTR, BCDTRUNC, BCDUTRUNC, and BCDUSHIFT instruction support (#154715) 
Support the following BCD format conversion builtins for PowerPC.

- `__builtin_bcdshift` – Shifts a packed decimal value by a specified
number of decimal digits.
- `__builtin_bcdshiftround` – Shifts a packed decimal value by a
specified number of decimal digits, with rounding applied.
- `__builtin_bcdtruncate` –Truncates a packed decimal value to a
specified number of digits.
- `__builtin_bcdunsignedtruncate` – Truncates a packed decimal value and
returns the result as an unsigned packed decimal.
- `__builtin_bcdunsignedshift` – Shifts an unsigned packed decimal value
by a specified number of digits.

> Note: This built-in functions are valid only when all following
conditions are met:
> -qarch is set to utilize POWER9 technology.
> The bcd.h file is included.

## Prototypes

```c
vector unsigned char __builtin_bcdshift(vector unsigned char, int, unsigned char);
vector unsigned char __builtin_bcdshiftround(vector unsigned char, int, unsigned char);
vector unsigned char __builtin_bcdtruncate(vector unsigned char, int, unsigned char);
vector unsigned char __builtin_bcdunsignedtruncate(vector unsigned char, int);
vector unsigned char __builtin_bcdunsignedshift(vector unsigned char, int);
```

---------
2026-01-21 21:34:06 +05:30

142 lines
4.5 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 \
; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown -mcpu=pwr9 \
; RUN: --ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-ibm-aix-xcoff \
; RUN: -ppc-asm-full-reg-names < %s | FileCheck %s
define <16 x i8> @test_bcdcopysign(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_bcdcopysign:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdcpsgn. v2, v2, v3
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdsetsign_imm0(<16 x i8> %a) {
; CHECK-LABEL: test_bcdsetsign_imm0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsetsgn. v2, v2, 0
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 0)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdsetsign_imm1(<16 x i8> %a) {
; CHECK-LABEL: test_bcdsetsign_imm1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: bcdsetsgn. v2, v2, 1
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8> %a, i32 1)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdshift_imm0(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdshift_imm0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcds. v2, v3, v2, 0
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 0)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdshift_imm1(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdshift_imm1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcds. v2, v3, v2, 1
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdshift(<16 x i8> %a, i32 %b, i32 1)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdshiftround_imm0(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdshiftround_imm0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcdsr. v2, v3, v2, 0
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 0)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdshiftround_imm1(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdshiftround_imm1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcdsr. v2, v3, v2, 1
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8> %a, i32 %b, i32 1)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdtruncate_imm0(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdtruncate_imm0:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcdtrunc. v2, v3, v2, 0
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 0)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdtruncate_imm1(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdtruncate_imm1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcdtrunc. v2, v3, v2, 1
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8> %a, i32 %b, i32 1)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdunsignedtruncate(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdunsignedtruncate:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcdutrunc. v2, v3, v2
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8> %a, i32 %b)
ret <16 x i8> %0
}
define <16 x i8> @test_bcdunsignedshift(<16 x i8> %a, i32 %b) {
; CHECK-LABEL: test_bcdunsignedshift:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrws vs35, [[REG:r[0-9]+]]
; CHECK-NEXT: bcdus. v2, v3, v2
; CHECK-NEXT: blr
entry:
%0 = tail call <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8> %a, i32 %b)
ret <16 x i8> %0
}
declare <16 x i8> @llvm.ppc.bcdcopysign(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.bcdsetsign(<16 x i8>, i32)
declare <16 x i8> @llvm.ppc.bcdshift(<16 x i8>, i32, i32)
declare <16 x i8> @llvm.ppc.bcdshiftround(<16 x i8>, i32, i32)
declare <16 x i8> @llvm.ppc.bcdtruncate(<16 x i8>, i32, i32)
declare <16 x i8> @llvm.ppc.bcdunsignedtruncate(<16 x i8>, i32)
declare <16 x i8> @llvm.ppc.bcdunsignedshift(<16 x i8>, i32)
Reference in New Issue View Git Blame Copy Permalink