shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/SystemZ/vec-abi-02.ll
Jonas Paulsson c999e9a4fe
[SystemZ] Support fp16 vector ABI and basic codegen. (#171066) 
- Make v8f16 a legal type so that arguments can be passed in vector
registers. Handle fp16 vectors so that they have the same ABI as other
fp vectors.

- Set the preferred vector action for fp16 vectors to "split". This will
scalarize all operations, which is not always necessary (like with
memory operations), but it avoids the superfluous operations that result
after first widening and then scalarizing a narrow vector (like v4f16).

Fixes #168992
2026-01-26 13:42:25 -06:00

1752 lines
56 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z16 | FileCheck %s
;
; Test passing vector arguments per the ABI for z16 (with vector support).
; The function names codify the element type and the size of the vector in
; bytes, just like in the clang test systemz-abi-vector.c
@global_char_1 = global <1 x i8> zeroinitializer, align 2
@global_char_8 = global <8 x i8> zeroinitializer, align 8
@global_char_16 = global <16 x i8> zeroinitializer, align 8
@global_char_32 = global <32 x i8> zeroinitializer, align 8
@global_short_2 = global <1 x i16> zeroinitializer, align 2
@global_short_8 = global <4 x i16> zeroinitializer, align 8
@global_short_16 = global <8 x i16> zeroinitializer, align 8
@global_int_4 = global <1 x i32> zeroinitializer, align 4
@global_int_8 = global <2 x i32> zeroinitializer, align 8
@global_int_16 = global <4 x i32> zeroinitializer, align 8
@global_int_32 = global <8 x i32> zeroinitializer, align 8
@global_long_8 = global <1 x i64> zeroinitializer, align 8
@global_long_16 = global <2 x i64> zeroinitializer, align 8
@global___int128_16 = global <1 x i128> zeroinitializer, align 8
@global___int128_32 = global <2 x i128> zeroinitializer, align 8
@global__Float16_2 = global <1 x half> zeroinitializer, align 2
@global__Float16_8 = global <4 x half> zeroinitializer, align 8
@global__Float16_16 = global <8 x half> zeroinitializer, align 8
@global__Float16_32 = global <16 x half> zeroinitializer, align 8
@global_float_4 = global <1 x float> zeroinitializer, align 4
@global_float_8 = global <2 x float> zeroinitializer, align 8
@global_float_16 = global <4 x float> zeroinitializer, align 8
@global_double_8 = global <1 x double> zeroinitializer, align 8
@global_double_16 = global <2 x double> zeroinitializer, align 8
@global_double_32 = global <4 x double> zeroinitializer, align 8
@global_long_double_16 = global <1 x fp128> zeroinitializer, align 8
@global_long_double_32 = global <2 x fp128> zeroinitializer, align 8
define void @takeAndStore_char_1(<1 x i8> noundef %x) {
; CHECK-LABEL: takeAndStore_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: vsteb %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x i8> %x, ptr @global_char_1, align 2
ret void
}
define void @takeAndStore_char_8(<8 x i8> noundef %x) {
; CHECK-LABEL: takeAndStore_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <8 x i8> %x, ptr @global_char_8, align 8
ret void
}
define void @takeAndStore_char_16(<16 x i8> noundef %x) {
; CHECK-LABEL: takeAndStore_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <16 x i8> %x, ptr @global_char_16, align 8
ret void
}
define void @takeAndStore_char_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vl %v1, 16(%r2), 3
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%x = load <32 x i8>, ptr %0, align 8
store <32 x i8> %x, ptr @global_char_32, align 8
ret void
}
define void @takeAndStore_short_2(<1 x i16> noundef %x) {
; CHECK-LABEL: takeAndStore_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: vsteh %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x i16> %x, ptr @global_short_2, align 2
ret void
}
define void @takeAndStore_short_8(<4 x i16> noundef %x) {
; CHECK-LABEL: takeAndStore_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <4 x i16> %x, ptr @global_short_8, align 8
ret void
}
define void @takeAndStore_short_16(<8 x i16> noundef %x) {
; CHECK-LABEL: takeAndStore_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <8 x i16> %x, ptr @global_short_16, align 8
ret void
}
define void @takeAndStore_int_4(<1 x i32> noundef %x) {
; CHECK-LABEL: takeAndStore_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: vstef %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x i32> %x, ptr @global_int_4, align 4
ret void
}
define void @takeAndStore_int_8(<2 x i32> noundef %x) {
; CHECK-LABEL: takeAndStore_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <2 x i32> %x, ptr @global_int_8, align 8
ret void
}
define void @takeAndStore_int_16(<4 x i32> noundef %x) {
; CHECK-LABEL: takeAndStore_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <4 x i32> %x, ptr @global_int_16, align 8
ret void
}
define void @takeAndStore_int_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vl %v1, 16(%r2), 3
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%x = load <8 x i32>, ptr %0, align 8
store <8 x i32> %x, ptr @global_int_32, align 8
ret void
}
define void @takeAndStore_long_8(<1 x i64> noundef %x) {
; CHECK-LABEL: takeAndStore_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x i64> %x, ptr @global_long_8, align 8
ret void
}
define void @takeAndStore_long_16(<2 x i64> noundef %x) {
; CHECK-LABEL: takeAndStore_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <2 x i64> %x, ptr @global_long_16, align 8
ret void
}
define void @takeAndStore___int128_16(<1 x i128> noundef %x) {
; CHECK-LABEL: takeAndStore___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <1 x i128> %x, ptr @global___int128_16, align 8
ret void
}
define void @takeAndStore___int128_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vl %v1, 16(%r2), 3
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%x = load <2 x i128>, ptr %0, align 8
store <2 x i128> %x, ptr @global___int128_32, align 8
ret void
}
define void @takeAndStore__Float16_2(<1 x half> noundef %x) {
; CHECK-LABEL: takeAndStore__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: vsteh %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x half> %x, ptr @global__Float16_2, align 2
ret void
}
define void @takeAndStore__Float16_8(<4 x half> noundef %x) {
; CHECK-LABEL: takeAndStore__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: vsteh %v24, 6(%r1), 3
; CHECK-NEXT: vsteh %v24, 4(%r1), 2
; CHECK-NEXT: vsteh %v24, 2(%r1), 1
; CHECK-NEXT: vsteh %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <4 x half> %x, ptr @global__Float16_8, align 8
ret void
}
define void @takeAndStore__Float16_16(<8 x half> noundef %x) {
; CHECK-LABEL: takeAndStore__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <8 x half> %x, ptr @global__Float16_16, align 8
ret void
}
define void @takeAndStore__Float16_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vl %v1, 16(%r2), 3
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%x = load <16 x half>, ptr %0, align 8
store <16 x half> %x, ptr @global__Float16_32, align 8
ret void
}
define void @takeAndStore_float_4(<1 x float> noundef %x) {
; CHECK-LABEL: takeAndStore_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: vstef %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x float> %x, ptr @global_float_4, align 4
ret void
}
define void @takeAndStore_float_8(<2 x float> noundef %x) {
; CHECK-LABEL: takeAndStore_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <2 x float> %x, ptr @global_float_8, align 8
ret void
}
define void @takeAndStore_float_16(<4 x float> noundef %x) {
; CHECK-LABEL: takeAndStore_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <4 x float> %x, ptr @global_float_16, align 8
ret void
}
define void @takeAndStore_double_8(<1 x double> noundef %x) {
; CHECK-LABEL: takeAndStore_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: br %r14
entry:
store <1 x double> %x, ptr @global_double_8, align 8
ret void
}
define void @takeAndStore_double_16(<2 x double> noundef %x) {
; CHECK-LABEL: takeAndStore_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <2 x double> %x, ptr @global_double_16, align 8
ret void
}
define void @takeAndStore_double_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vl %v1, 16(%r2), 3
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%x = load <4 x double>, ptr %0, align 8
store <4 x double> %x, ptr @global_double_32, align 8
ret void
}
define void @takeAndStore_long_double_16(<1 x fp128> noundef %x) {
; CHECK-LABEL: takeAndStore_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
store <1 x fp128> %x, ptr @global_long_double_16, align 8
ret void
}
define void @takeAndStore_long_double_32(ptr noundef readonly captures(none) dead_on_return %0) {
; CHECK-LABEL: takeAndStore_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vl %v0, 0(%r2), 3
; CHECK-NEXT: vl %v1, 16(%r2), 3
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%x = load <2 x fp128>, ptr %0, align 8
store <2 x fp128> %x, ptr @global_long_double_32, align 8
ret void
}
define <1 x i8> @loadAndReturn_char_1() {
; CHECK-LABEL: loadAndReturn_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: vlrepb %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i8>, ptr @global_char_1, align 2
ret <1 x i8> %0
}
define <8 x i8> @loadAndReturn_char_8() {
; CHECK-LABEL: loadAndReturn_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x i8>, ptr @global_char_8, align 8
ret <8 x i8> %0
}
define <16 x i8> @loadAndReturn_char_16() {
; CHECK-LABEL: loadAndReturn_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <16 x i8>, ptr @global_char_16, align 8
ret <16 x i8> %0
}
define void @loadAndReturn_char_32(ptr dead_on_unwind noalias writable writeonly sret(<32 x i8>) align 8 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: vst %v1, 16(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <32 x i8>, ptr @global_char_32, align 8
store <32 x i8> %0, ptr %agg.result, align 8
ret void
}
define <1 x i16> @loadAndReturn_short_2() {
; CHECK-LABEL: loadAndReturn_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: vlreph %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i16>, ptr @global_short_2, align 2
ret <1 x i16> %0
}
define <4 x i16> @loadAndReturn_short_8() {
; CHECK-LABEL: loadAndReturn_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x i16>, ptr @global_short_8, align 8
ret <4 x i16> %0
}
define <8 x i16> @loadAndReturn_short_16() {
; CHECK-LABEL: loadAndReturn_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x i16>, ptr @global_short_16, align 8
ret <8 x i16> %0
}
define <1 x i32> @loadAndReturn_int_4() {
; CHECK-LABEL: loadAndReturn_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: vlrepf %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i32>, ptr @global_int_4, align 4
ret <1 x i32> %0
}
define <2 x i32> @loadAndReturn_int_8() {
; CHECK-LABEL: loadAndReturn_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x i32>, ptr @global_int_8, align 8
ret <2 x i32> %0
}
define <4 x i32> @loadAndReturn_int_16() {
; CHECK-LABEL: loadAndReturn_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x i32>, ptr @global_int_16, align 8
ret <4 x i32> %0
}
define void @loadAndReturn_int_32(ptr dead_on_unwind noalias writable writeonly sret(<8 x i32>) align 8 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: vst %v1, 16(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x i32>, ptr @global_int_32, align 8
store <8 x i32> %0, ptr %agg.result, align 8
ret void
}
define <1 x i64> @loadAndReturn_long_8() {
; CHECK-LABEL: loadAndReturn_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i64>, ptr @global_long_8, align 8
ret <1 x i64> %0
}
define <2 x i64> @loadAndReturn_long_16() {
; CHECK-LABEL: loadAndReturn_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x i64>, ptr @global_long_16, align 8
ret <2 x i64> %0
}
define <1 x i128> @loadAndReturn___int128_16() {
; CHECK-LABEL: loadAndReturn___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x i128>, ptr @global___int128_16, align 8
ret <1 x i128> %0
}
define void @loadAndReturn___int128_32(ptr dead_on_unwind noalias writable writeonly sret(<2 x i128>) align 8 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: vst %v1, 16(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x i128>, ptr @global___int128_32, align 8
store <2 x i128> %0, ptr %agg.result, align 8
ret void
}
define <1 x half> @loadAndReturn__Float16_2() {
; CHECK-LABEL: loadAndReturn__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: vlreph %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x half>, ptr @global__Float16_2, align 2
ret <1 x half> %0
}
define <4 x half> @loadAndReturn__Float16_8() {
; CHECK-LABEL: loadAndReturn__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: vlreph %v0, 0(%r1)
; CHECK-NEXT: vlreph %v1, 2(%r1)
; CHECK-NEXT: vlreph %v2, 4(%r1)
; CHECK-NEXT: vlreph %v3, 6(%r1)
; CHECK-NEXT: vmrhh %v2, %v2, %v3
; CHECK-NEXT: vmrhh %v0, %v0, %v1
; CHECK-NEXT: vmrhf %v0, %v0, %v2
; CHECK-NEXT: vmrhg %v24, %v0, %v0
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x half>, ptr @global__Float16_8, align 8
ret <4 x half> %0
}
define <8 x half> @loadAndReturn__Float16_16() {
; CHECK-LABEL: loadAndReturn__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <8 x half>, ptr @global__Float16_16, align 8
ret <8 x half> %0
}
define void @loadAndReturn__Float16_32(ptr dead_on_unwind noalias writable writeonly sret(<16 x half>) align 8 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: vst %v1, 16(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <16 x half>, ptr @global__Float16_32, align 8
store <16 x half> %0, ptr %agg.result, align 8
ret void
}
define <1 x float> @loadAndReturn_float_4() {
; CHECK-LABEL: loadAndReturn_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: vlrepf %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x float>, ptr @global_float_4, align 4
ret <1 x float> %0
}
define <2 x float> @loadAndReturn_float_8() {
; CHECK-LABEL: loadAndReturn_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x float>, ptr @global_float_8, align 8
ret <2 x float> %0
}
define <4 x float> @loadAndReturn_float_16() {
; CHECK-LABEL: loadAndReturn_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x float>, ptr @global_float_16, align 8
ret <4 x float> %0
}
define <1 x double> @loadAndReturn_double_8() {
; CHECK-LABEL: loadAndReturn_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x double>, ptr @global_double_8, align 8
ret <1 x double> %0
}
define <2 x double> @loadAndReturn_double_16() {
; CHECK-LABEL: loadAndReturn_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x double>, ptr @global_double_16, align 8
ret <2 x double> %0
}
define void @loadAndReturn_double_32(ptr dead_on_unwind noalias writable writeonly sret(<4 x double>) align 8 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: vst %v1, 16(%r2), 3
; CHECK-NEXT: vst %v0, 0(%r2), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <4 x double>, ptr @global_double_32, align 8
store <4 x double> %0, ptr %agg.result, align 8
ret void
}
define <1 x fp128> @loadAndReturn_long_double_16() {
; CHECK-LABEL: loadAndReturn_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: br %r14
entry:
%0 = load <1 x fp128>, ptr @global_long_double_16, align 8
ret <1 x fp128> %0
}
define void @loadAndReturn_long_double_32(ptr dead_on_unwind noalias writable writeonly sret(<2 x fp128>) align 8 captures(none) initializes((0, 32)) %agg.result) {
; CHECK-LABEL: loadAndReturn_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: mvc 16(16,%r2), 16(%r1)
; CHECK-NEXT: mvc 0(16,%r2), 0(%r1)
; CHECK-NEXT: br %r14
entry:
%0 = load <2 x fp128>, ptr @global_long_double_32, align 8
store <2 x fp128> %0, ptr %agg.result, align 8
ret void
}
define void @loadAndPass_char_1() {
; CHECK-LABEL: loadAndPass_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: vlrepb %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_char_1@PLT
entry:
%0 = load <1 x i8>, ptr @global_char_1, align 2
tail call void @passCallee_char_1(<1 x i8> noundef %0)
ret void
}
declare void @passCallee_char_1(<1 x i8> noundef)
define void @loadAndPass_char_8() {
; CHECK-LABEL: loadAndPass_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_char_8@PLT
entry:
%0 = load <8 x i8>, ptr @global_char_8, align 8
tail call void @passCallee_char_8(<8 x i8> noundef %0)
ret void
}
declare void @passCallee_char_8(<8 x i8> noundef)
define void @loadAndPass_char_16() {
; CHECK-LABEL: loadAndPass_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_char_16@PLT
entry:
%0 = load <16 x i8>, ptr @global_char_16, align 8
tail call void @passCallee_char_16(<16 x i8> noundef %0)
ret void
}
declare void @passCallee_char_16(<16 x i8> noundef)
define void @loadAndPass_char_32() {
; CHECK-LABEL: loadAndPass_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: vst %v1, 176(%r15), 3
; CHECK-NEXT: vst %v0, 160(%r15), 3
; CHECK-NEXT: brasl %r14, passCallee_char_32@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <32 x i8>, align 8
%0 = load <32 x i8>, ptr @global_char_32, align 8
store <32 x i8> %0, ptr %byval-temp, align 8
call void @passCallee_char_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_char_32(ptr noundef dead_on_return)
define void @loadAndPass_short_2() {
; CHECK-LABEL: loadAndPass_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: vlreph %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_short_2@PLT
entry:
%0 = load <1 x i16>, ptr @global_short_2, align 2
tail call void @passCallee_short_2(<1 x i16> noundef %0)
ret void
}
declare void @passCallee_short_2(<1 x i16> noundef)
define void @loadAndPass_short_8() {
; CHECK-LABEL: loadAndPass_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_short_8@PLT
entry:
%0 = load <4 x i16>, ptr @global_short_8, align 8
tail call void @passCallee_short_8(<4 x i16> noundef %0)
ret void
}
declare void @passCallee_short_8(<4 x i16> noundef)
define void @loadAndPass_short_16() {
; CHECK-LABEL: loadAndPass_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_short_16@PLT
entry:
%0 = load <8 x i16>, ptr @global_short_16, align 8
tail call void @passCallee_short_16(<8 x i16> noundef %0)
ret void
}
declare void @passCallee_short_16(<8 x i16> noundef)
define void @loadAndPass_int_4() {
; CHECK-LABEL: loadAndPass_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: vlrepf %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_int_4@PLT
entry:
%0 = load <1 x i32>, ptr @global_int_4, align 4
tail call void @passCallee_int_4(<1 x i32> noundef %0)
ret void
}
declare void @passCallee_int_4(<1 x i32> noundef)
define void @loadAndPass_int_8() {
; CHECK-LABEL: loadAndPass_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_int_8@PLT
entry:
%0 = load <2 x i32>, ptr @global_int_8, align 8
tail call void @passCallee_int_8(<2 x i32> noundef %0)
ret void
}
declare void @passCallee_int_8(<2 x i32> noundef)
define void @loadAndPass_int_16() {
; CHECK-LABEL: loadAndPass_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_int_16@PLT
entry:
%0 = load <4 x i32>, ptr @global_int_16, align 8
tail call void @passCallee_int_16(<4 x i32> noundef %0)
ret void
}
declare void @passCallee_int_16(<4 x i32> noundef)
define void @loadAndPass_int_32() {
; CHECK-LABEL: loadAndPass_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: vst %v1, 176(%r15), 3
; CHECK-NEXT: vst %v0, 160(%r15), 3
; CHECK-NEXT: brasl %r14, passCallee_int_32@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <8 x i32>, align 8
%0 = load <8 x i32>, ptr @global_int_32, align 8
store <8 x i32> %0, ptr %byval-temp, align 8
call void @passCallee_int_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_int_32(ptr noundef dead_on_return)
define void @loadAndPass_long_8() {
; CHECK-LABEL: loadAndPass_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_long_8@PLT
entry:
%0 = load <1 x i64>, ptr @global_long_8, align 8
tail call void @passCallee_long_8(<1 x i64> noundef %0)
ret void
}
declare void @passCallee_long_8(<1 x i64> noundef)
define void @loadAndPass_long_16() {
; CHECK-LABEL: loadAndPass_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_long_16@PLT
entry:
%0 = load <2 x i64>, ptr @global_long_16, align 8
tail call void @passCallee_long_16(<2 x i64> noundef %0)
ret void
}
declare void @passCallee_long_16(<2 x i64> noundef)
define void @loadAndPass___int128_16() {
; CHECK-LABEL: loadAndPass___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee___int128_16@PLT
entry:
%0 = load <1 x i128>, ptr @global___int128_16, align 8
tail call void @passCallee___int128_16(<1 x i128> noundef %0)
ret void
}
declare void @passCallee___int128_16(<1 x i128> noundef)
define void @loadAndPass___int128_32() {
; CHECK-LABEL: loadAndPass___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: vst %v1, 176(%r15), 3
; CHECK-NEXT: vst %v0, 160(%r15), 3
; CHECK-NEXT: brasl %r14, passCallee___int128_32@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x i128>, align 8
%0 = load <2 x i128>, ptr @global___int128_32, align 8
store <2 x i128> %0, ptr %byval-temp, align 8
call void @passCallee___int128_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee___int128_32(ptr noundef dead_on_return)
define void @loadAndPass__Float16_2() {
; CHECK-LABEL: loadAndPass__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: vlreph %v24, 0(%r1)
; CHECK-NEXT: jg passCallee__Float16_2@PLT
entry:
%0 = load <1 x half>, ptr @global__Float16_2, align 2
tail call void @passCallee__Float16_2(<1 x half> noundef %0)
ret void
}
declare void @passCallee__Float16_2(<1 x half> noundef)
define void @loadAndPass__Float16_8() {
; CHECK-LABEL: loadAndPass__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: vlreph %v0, 0(%r1)
; CHECK-NEXT: vlreph %v1, 2(%r1)
; CHECK-NEXT: vlreph %v2, 4(%r1)
; CHECK-NEXT: vlreph %v3, 6(%r1)
; CHECK-NEXT: vmrhh %v2, %v2, %v3
; CHECK-NEXT: vmrhh %v0, %v0, %v1
; CHECK-NEXT: vmrhf %v0, %v0, %v2
; CHECK-NEXT: vmrhg %v24, %v0, %v0
; CHECK-NEXT: jg passCallee__Float16_8@PLT
entry:
%0 = load <4 x half>, ptr @global__Float16_8, align 8
tail call void @passCallee__Float16_8(<4 x half> noundef %0)
ret void
}
declare void @passCallee__Float16_8(<4 x half> noundef)
define void @loadAndPass__Float16_16() {
; CHECK-LABEL: loadAndPass__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee__Float16_16@PLT
entry:
%0 = load <8 x half>, ptr @global__Float16_16, align 8
tail call void @passCallee__Float16_16(<8 x half> noundef %0)
ret void
}
declare void @passCallee__Float16_16(<8 x half> noundef)
define void @loadAndPass__Float16_32() {
; CHECK-LABEL: loadAndPass__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: vst %v1, 176(%r15), 3
; CHECK-NEXT: vst %v0, 160(%r15), 3
; CHECK-NEXT: brasl %r14, passCallee__Float16_32@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <16 x half>, align 8
%0 = load <16 x half>, ptr @global__Float16_32, align 8
store <16 x half> %0, ptr %byval-temp, align 8
call void @passCallee__Float16_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee__Float16_32(ptr noundef dead_on_return)
define void @loadAndPass_float_4() {
; CHECK-LABEL: loadAndPass_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: vlrepf %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_float_4@PLT
entry:
%0 = load <1 x float>, ptr @global_float_4, align 4
tail call void @passCallee_float_4(<1 x float> noundef %0)
ret void
}
declare void @passCallee_float_4(<1 x float> noundef)
define void @loadAndPass_float_8() {
; CHECK-LABEL: loadAndPass_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_float_8@PLT
entry:
%0 = load <2 x float>, ptr @global_float_8, align 8
tail call void @passCallee_float_8(<2 x float> noundef %0)
ret void
}
declare void @passCallee_float_8(<2 x float> noundef)
define void @loadAndPass_float_16() {
; CHECK-LABEL: loadAndPass_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_float_16@PLT
entry:
%0 = load <4 x float>, ptr @global_float_16, align 8
tail call void @passCallee_float_16(<4 x float> noundef %0)
ret void
}
declare void @passCallee_float_16(<4 x float> noundef)
define void @loadAndPass_double_8() {
; CHECK-LABEL: loadAndPass_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: vlrepg %v24, 0(%r1)
; CHECK-NEXT: jg passCallee_double_8@PLT
entry:
%0 = load <1 x double>, ptr @global_double_8, align 8
tail call void @passCallee_double_8(<1 x double> noundef %0)
ret void
}
declare void @passCallee_double_8(<1 x double> noundef)
define void @loadAndPass_double_16() {
; CHECK-LABEL: loadAndPass_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_double_16@PLT
entry:
%0 = load <2 x double>, ptr @global_double_16, align 8
tail call void @passCallee_double_16(<2 x double> noundef %0)
ret void
}
declare void @passCallee_double_16(<2 x double> noundef)
define void @loadAndPass_double_32() {
; CHECK-LABEL: loadAndPass_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: vl %v0, 0(%r1), 3
; CHECK-NEXT: vl %v1, 16(%r1), 3
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: vst %v1, 176(%r15), 3
; CHECK-NEXT: vst %v0, 160(%r15), 3
; CHECK-NEXT: brasl %r14, passCallee_double_32@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <4 x double>, align 8
%0 = load <4 x double>, ptr @global_double_32, align 8
store <4 x double> %0, ptr %byval-temp, align 8
call void @passCallee_double_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_double_32(ptr noundef dead_on_return)
define void @loadAndPass_long_double_16() {
; CHECK-LABEL: loadAndPass_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: vl %v24, 0(%r1), 3
; CHECK-NEXT: jg passCallee_long_double_16@PLT
entry:
%0 = load <1 x fp128>, ptr @global_long_double_16, align 8
tail call void @passCallee_long_double_16(<1 x fp128> noundef %0)
ret void
}
declare void @passCallee_long_double_16(<1 x fp128> noundef)
define void @loadAndPass_long_double_32() {
; CHECK-LABEL: loadAndPass_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: mvc 176(16,%r15), 16(%r1)
; CHECK-NEXT: mvc 160(16,%r15), 0(%r1)
; CHECK-NEXT: brasl %r14, passCallee_long_double_32@PLT
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%byval-temp = alloca <2 x fp128>, align 8
%0 = load <2 x fp128>, ptr @global_long_double_32, align 8
store <2 x fp128> %0, ptr %byval-temp, align 8
call void @passCallee_long_double_32(ptr noundef nonnull dead_on_return %byval-temp)
ret void
}
declare void @passCallee_long_double_32(ptr noundef dead_on_return)
define void @receiveAndStore_char_1() {
; CHECK-LABEL: receiveAndStore_char_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_char_1@PLT
; CHECK-NEXT: lgrl %r1, global_char_1@GOT
; CHECK-NEXT: vsteb %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x i8> @retCallee_char_1()
store <1 x i8> %call, ptr @global_char_1, align 2
ret void
}
declare <1 x i8> @retCallee_char_1()
define void @receiveAndStore_char_8() {
; CHECK-LABEL: receiveAndStore_char_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_char_8@PLT
; CHECK-NEXT: lgrl %r1, global_char_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <8 x i8> @retCallee_char_8()
store <8 x i8> %call, ptr @global_char_8, align 8
ret void
}
declare <8 x i8> @retCallee_char_8()
define void @receiveAndStore_char_16() {
; CHECK-LABEL: receiveAndStore_char_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_char_16@PLT
; CHECK-NEXT: lgrl %r1, global_char_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <16 x i8> @retCallee_char_16()
store <16 x i8> %call, ptr @global_char_16, align 8
ret void
}
declare <16 x i8> @retCallee_char_16()
define void @receiveAndStore_char_32() {
; CHECK-LABEL: receiveAndStore_char_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_char_32@PLT
; CHECK-NEXT: vl %v0, 160(%r15), 3
; CHECK-NEXT: vl %v1, 176(%r15), 3
; CHECK-NEXT: lgrl %r1, global_char_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <32 x i8>, align 8
call void @retCallee_char_32(ptr dead_on_unwind nonnull writable sret(<32 x i8>) align 8 %tmp)
%0 = load <32 x i8>, ptr %tmp, align 8
store <32 x i8> %0, ptr @global_char_32, align 8
ret void
}
declare void @retCallee_char_32(ptr dead_on_unwind writable sret(<32 x i8>) align 8)
define void @receiveAndStore_short_2() {
; CHECK-LABEL: receiveAndStore_short_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_short_2@PLT
; CHECK-NEXT: lgrl %r1, global_short_2@GOT
; CHECK-NEXT: vsteh %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x i16> @retCallee_short_2()
store <1 x i16> %call, ptr @global_short_2, align 2
ret void
}
declare <1 x i16> @retCallee_short_2()
define void @receiveAndStore_short_8() {
; CHECK-LABEL: receiveAndStore_short_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_short_8@PLT
; CHECK-NEXT: lgrl %r1, global_short_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <4 x i16> @retCallee_short_8()
store <4 x i16> %call, ptr @global_short_8, align 8
ret void
}
declare <4 x i16> @retCallee_short_8()
define void @receiveAndStore_short_16() {
; CHECK-LABEL: receiveAndStore_short_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_short_16@PLT
; CHECK-NEXT: lgrl %r1, global_short_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <8 x i16> @retCallee_short_16()
store <8 x i16> %call, ptr @global_short_16, align 8
ret void
}
declare <8 x i16> @retCallee_short_16()
define void @receiveAndStore_int_4() {
; CHECK-LABEL: receiveAndStore_int_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_int_4@PLT
; CHECK-NEXT: lgrl %r1, global_int_4@GOT
; CHECK-NEXT: vstef %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x i32> @retCallee_int_4()
store <1 x i32> %call, ptr @global_int_4, align 4
ret void
}
declare <1 x i32> @retCallee_int_4()
define void @receiveAndStore_int_8() {
; CHECK-LABEL: receiveAndStore_int_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_int_8@PLT
; CHECK-NEXT: lgrl %r1, global_int_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <2 x i32> @retCallee_int_8()
store <2 x i32> %call, ptr @global_int_8, align 8
ret void
}
declare <2 x i32> @retCallee_int_8()
define void @receiveAndStore_int_16() {
; CHECK-LABEL: receiveAndStore_int_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_int_16@PLT
; CHECK-NEXT: lgrl %r1, global_int_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <4 x i32> @retCallee_int_16()
store <4 x i32> %call, ptr @global_int_16, align 8
ret void
}
declare <4 x i32> @retCallee_int_16()
define void @receiveAndStore_int_32() {
; CHECK-LABEL: receiveAndStore_int_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_int_32@PLT
; CHECK-NEXT: vl %v0, 160(%r15), 3
; CHECK-NEXT: vl %v1, 176(%r15), 3
; CHECK-NEXT: lgrl %r1, global_int_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <8 x i32>, align 8
call void @retCallee_int_32(ptr dead_on_unwind nonnull writable sret(<8 x i32>) align 8 %tmp)
%0 = load <8 x i32>, ptr %tmp, align 8
store <8 x i32> %0, ptr @global_int_32, align 8
ret void
}
declare void @retCallee_int_32(ptr dead_on_unwind writable sret(<8 x i32>) align 8)
define void @receiveAndStore_long_8() {
; CHECK-LABEL: receiveAndStore_long_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_long_8@PLT
; CHECK-NEXT: lgrl %r1, global_long_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x i64> @retCallee_long_8()
store <1 x i64> %call, ptr @global_long_8, align 8
ret void
}
declare <1 x i64> @retCallee_long_8()
define void @receiveAndStore_long_16() {
; CHECK-LABEL: receiveAndStore_long_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_long_16@PLT
; CHECK-NEXT: lgrl %r1, global_long_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <2 x i64> @retCallee_long_16()
store <2 x i64> %call, ptr @global_long_16, align 8
ret void
}
declare <2 x i64> @retCallee_long_16()
define void @receiveAndStore___int128_16() {
; CHECK-LABEL: receiveAndStore___int128_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee___int128_16@PLT
; CHECK-NEXT: lgrl %r1, global___int128_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x i128> @retCallee___int128_16()
store <1 x i128> %call, ptr @global___int128_16, align 8
ret void
}
declare <1 x i128> @retCallee___int128_16()
define void @receiveAndStore___int128_32() {
; CHECK-LABEL: receiveAndStore___int128_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee___int128_32@PLT
; CHECK-NEXT: vl %v0, 160(%r15), 3
; CHECK-NEXT: vl %v1, 176(%r15), 3
; CHECK-NEXT: lgrl %r1, global___int128_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x i128>, align 8
call void @retCallee___int128_32(ptr dead_on_unwind nonnull writable sret(<2 x i128>) align 8 %tmp)
%0 = load <2 x i128>, ptr %tmp, align 8
store <2 x i128> %0, ptr @global___int128_32, align 8
ret void
}
declare void @retCallee___int128_32(ptr dead_on_unwind writable sret(<2 x i128>) align 8)
define void @receiveAndStore__Float16_2() {
; CHECK-LABEL: receiveAndStore__Float16_2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee__Float16_2@PLT
; CHECK-NEXT: lgrl %r1, global__Float16_2@GOT
; CHECK-NEXT: vsteh %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x half> @retCallee__Float16_2()
store <1 x half> %call, ptr @global__Float16_2, align 2
ret void
}
declare <1 x half> @retCallee__Float16_2()
define void @receiveAndStore__Float16_8() {
; CHECK-LABEL: receiveAndStore__Float16_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee__Float16_8@PLT
; CHECK-NEXT: lgrl %r1, global__Float16_8@GOT
; CHECK-NEXT: vsteh %v24, 6(%r1), 3
; CHECK-NEXT: vsteh %v24, 4(%r1), 2
; CHECK-NEXT: vsteh %v24, 2(%r1), 1
; CHECK-NEXT: vsteh %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <4 x half> @retCallee__Float16_8()
store <4 x half> %call, ptr @global__Float16_8, align 8
ret void
}
declare <4 x half> @retCallee__Float16_8()
define void @receiveAndStore__Float16_16() {
; CHECK-LABEL: receiveAndStore__Float16_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee__Float16_16@PLT
; CHECK-NEXT: lgrl %r1, global__Float16_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <8 x half> @retCallee__Float16_16()
store <8 x half> %call, ptr @global__Float16_16, align 8
ret void
}
declare <8 x half> @retCallee__Float16_16()
define void @receiveAndStore__Float16_32() {
; CHECK-LABEL: receiveAndStore__Float16_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee__Float16_32@PLT
; CHECK-NEXT: vl %v0, 160(%r15), 3
; CHECK-NEXT: vl %v1, 176(%r15), 3
; CHECK-NEXT: lgrl %r1, global__Float16_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <16 x half>, align 8
call void @retCallee__Float16_32(ptr dead_on_unwind nonnull writable sret(<16 x half>) align 8 %tmp)
%0 = load <16 x half>, ptr %tmp, align 8
store <16 x half> %0, ptr @global__Float16_32, align 8
ret void
}
declare void @retCallee__Float16_32(ptr dead_on_unwind writable sret(<16 x half>) align 8)
define void @receiveAndStore_float_4() {
; CHECK-LABEL: receiveAndStore_float_4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_float_4@PLT
; CHECK-NEXT: lgrl %r1, global_float_4@GOT
; CHECK-NEXT: vstef %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x float> @retCallee_float_4()
store <1 x float> %call, ptr @global_float_4, align 4
ret void
}
declare <1 x float> @retCallee_float_4()
define void @receiveAndStore_float_8() {
; CHECK-LABEL: receiveAndStore_float_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_float_8@PLT
; CHECK-NEXT: lgrl %r1, global_float_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <2 x float> @retCallee_float_8()
store <2 x float> %call, ptr @global_float_8, align 8
ret void
}
declare <2 x float> @retCallee_float_8()
define void @receiveAndStore_float_16() {
; CHECK-LABEL: receiveAndStore_float_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_float_16@PLT
; CHECK-NEXT: lgrl %r1, global_float_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <4 x float> @retCallee_float_16()
store <4 x float> %call, ptr @global_float_16, align 8
ret void
}
declare <4 x float> @retCallee_float_16()
define void @receiveAndStore_double_8() {
; CHECK-LABEL: receiveAndStore_double_8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_double_8@PLT
; CHECK-NEXT: lgrl %r1, global_double_8@GOT
; CHECK-NEXT: vsteg %v24, 0(%r1), 0
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x double> @retCallee_double_8()
store <1 x double> %call, ptr @global_double_8, align 8
ret void
}
declare <1 x double> @retCallee_double_8()
define void @receiveAndStore_double_16() {
; CHECK-LABEL: receiveAndStore_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_double_16@PLT
; CHECK-NEXT: lgrl %r1, global_double_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <2 x double> @retCallee_double_16()
store <2 x double> %call, ptr @global_double_16, align 8
ret void
}
declare <2 x double> @retCallee_double_16()
define void @receiveAndStore_double_32() {
; CHECK-LABEL: receiveAndStore_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_double_32@PLT
; CHECK-NEXT: vl %v0, 160(%r15), 3
; CHECK-NEXT: vl %v1, 176(%r15), 3
; CHECK-NEXT: lgrl %r1, global_double_32@GOT
; CHECK-NEXT: vst %v1, 16(%r1), 3
; CHECK-NEXT: vst %v0, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <4 x double>, align 8
call void @retCallee_double_32(ptr dead_on_unwind nonnull writable sret(<4 x double>) align 8 %tmp)
%0 = load <4 x double>, ptr %tmp, align 8
store <4 x double> %0, ptr @global_double_32, align 8
ret void
}
declare void @retCallee_double_32(ptr dead_on_unwind writable sret(<4 x double>) align 8)
define void @receiveAndStore_long_double_16() {
; CHECK-LABEL: receiveAndStore_long_double_16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: .cfi_def_cfa_offset 320
; CHECK-NEXT: brasl %r14, retCallee_long_double_16@PLT
; CHECK-NEXT: lgrl %r1, global_long_double_16@GOT
; CHECK-NEXT: vst %v24, 0(%r1), 3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: br %r14
entry:
%call = tail call <1 x fp128> @retCallee_long_double_16()
store <1 x fp128> %call, ptr @global_long_double_16, align 8
ret void
}
declare <1 x fp128> @retCallee_long_double_16()
define void @receiveAndStore_long_double_32() {
; CHECK-LABEL: receiveAndStore_long_double_32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: .cfi_offset %r14, -48
; CHECK-NEXT: .cfi_offset %r15, -40
; CHECK-NEXT: aghi %r15, -192
; CHECK-NEXT: .cfi_def_cfa_offset 352
; CHECK-NEXT: la %r2, 160(%r15)
; CHECK-NEXT: brasl %r14, retCallee_long_double_32@PLT
; CHECK-NEXT: lgrl %r1, global_long_double_32@GOT
; CHECK-NEXT: mvc 16(16,%r1), 176(%r15)
; CHECK-NEXT: mvc 0(16,%r1), 160(%r15)
; CHECK-NEXT: lmg %r14, %r15, 304(%r15)
; CHECK-NEXT: br %r14
entry:
%tmp = alloca <2 x fp128>, align 8
call void @retCallee_long_double_32(ptr dead_on_unwind nonnull writable sret(<2 x fp128>) align 8 %tmp)
%0 = load <2 x fp128>, ptr %tmp, align 8
store <2 x fp128> %0, ptr @global_long_double_32, align 8
ret void
}
declare void @retCallee_long_double_32(ptr dead_on_unwind writable sret(<2 x fp128>) align 8)
Reference in New Issue View Git Blame Copy Permalink