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llvm-project/llvm/test/Transforms/AggressiveInstCombine
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Nikita Popov 4167b285e2
[AggressiveInstCombine] Create zext during store merge (#181125) 
The top extracted value can include shifted-in zero bits. In that case
we should emit a zext before the new store.

Fixes https://github.com/llvm/llvm-project/issues/181117.
2026-02-12 14:41:00 +01:00
..
AArch64
[AggressiveInstCombine] Allow load folding for root inst with multiple uses. (#176101)
2026-01-16 13:19:50 -06:00
AMDGPU
[AggressiveInstCombine] Allow load folding for root inst with multiple uses. (#176101)
2026-01-16 13:19:50 -06:00
ARM
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X86
[AggressiveInstCombine] Create zext during store merge (#181125)
2026-02-12 14:41:00 +01:00
dbgloc-memchr.ll
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funnel.ll
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inline-strcmp-debugloc.ll
[profcheck] Add unknown branch weights for inlined strcmp/strncmp (#160455)
2025-09-25 20:11:30 -07:00
logic-combine.ll
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lower-table-based-cttz-basics.ll
[profcheck] Add heuristical profile metadata for lowering table-based cttz. (#161898)
2025-10-08 19:50:28 -07:00
lower-table-based-cttz-dereferencing-pointer.ll
[profcheck] Add heuristical profile metadata for lowering table-based cttz. (#161898)
2025-10-08 19:50:28 -07:00
lower-table-based-cttz-non-argument-value.ll
[profcheck] Add heuristical profile metadata for lowering table-based cttz. (#161898)
2025-10-08 19:50:28 -07:00
lower-table-based-cttz-zero-element.ll
[profcheck] Add heuristical profile metadata for lowering table-based cttz. (#161898)
2025-10-08 19:50:28 -07:00
masked-cmp.ll
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memchr.ll
[AggressiveInstCombine] Avoid implicit truncation
2026-01-14 10:44:47 +01:00
negative-lower-table-based-cttz.ll
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or-shift-chain.ll
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patterned-load.ll
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popcount.ll
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pr50555.ll
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rotate.ll
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strncmp-1.ll
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strncmp-2.ll
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trunc_ashr.ll
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trunc_assume.ll
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trunc_const_expr.ll
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trunc_lshr.ll
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trunc_multi_uses.ll
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trunc_phi.ll
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trunc_select_cmp.ll
[profcheck] Propagate profile metadata in trunc(select) transform (#162406)
2025-10-09 13:41:53 -07:00
trunc_select.ll
[profcheck] Propagate profile metadata in trunc(select) transform (#162406)
2025-10-09 13:41:53 -07:00
trunc_shl.ll
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trunc_udivrem.ll
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trunc_unreachable_bb.ll
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trunc_vector_instrs.ll
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umulh_carry4.ll
[AggressiveInstCombine] Match long high-half multiply (#168396)
2025-11-27 07:22:41 +00:00
umulh_carry.ll
[AggressiveInstCombine] Match long high-half multiply (#168396)
2025-11-27 07:22:41 +00:00
umulh_ladder4.ll
[AggressiveInstCombine] Match long high-half multiply (#168396)
2025-11-27 07:22:41 +00:00
umulh_ladder.ll
[AggressiveInstCombine] Match long high-half multiply (#168396)
2025-11-27 07:22:41 +00:00
vector-or-load.ll
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