c752bb9203
When reviewing another change, I noticed that we were failing to infer samsign for two cases: 1) an unsigned comparison, and 2) when both arguments were known negative. Using CVP and InstCombine as a reference, we need to be careful to not allow eq/ne comparisons. I'm a bit unclear on the why of that, and for now am going with the low risk change. I may return to investigate that in a follow up. Compile time results look like noise to me, see: https://llvm-compile-time-tracker.com/compare.php?from=49a978712893fcf9e5f40ac488315d029cf15d3d&to=2ddb263604fd7d538e09dc1f805ebc30eb3ffab0&stat=instructions:u
101 lines
3.0 KiB
LLVM
101 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -passes=indvars -S < %s | FileCheck %s
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declare i1 @cond()
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define i32 @test_01(ptr %p, ptr %s) {
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; CHECK-LABEL: @test_01(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[START:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0:![0-9]+]]
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; CHECK-NEXT: [[END:%.*]] = load i32, ptr [[S:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[C1:%.*]] = icmp samesign ult i32 [[IV]], [[END]]
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; CHECK-NEXT: br i1 [[C1]], label [[GUARDED:%.*]], label [[SIDE_EXIT:%.*]]
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; CHECK: guarded:
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; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[SIDE_EXIT]]
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; CHECK: backedge:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[LOOP_COND:%.*]] = call i1 @cond()
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 1
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; CHECK: side_exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%start = load i32, ptr %p, !range !0
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%end = load i32, ptr %s, !range !0
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %backedge]
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%c1 = icmp slt i32 %iv, %end
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br i1 %c1, label %guarded, label %side_exit
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guarded:
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%c2 = icmp ult i32 %iv, %end
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br i1 %c2, label %backedge, label %side_exit
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backedge:
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%iv.next = add nuw nsw i32 %iv, 1
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%loop.cond = call i1 @cond()
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br i1 %loop.cond, label %loop, label %exit
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exit:
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ret i32 1
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side_exit:
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ret i32 0
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}
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define i32 @test_02(ptr %p, ptr %s) {
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; CHECK-LABEL: @test_02(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[START:%.*]] = load i32, ptr [[P:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: [[END:%.*]] = load i32, ptr [[S:%.*]], align 4, !range [[RNG0]]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[START]], [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[C1:%.*]] = icmp samesign ult i32 [[IV]], [[END]]
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; CHECK-NEXT: br i1 [[C1]], label [[GUARDED:%.*]], label [[SIDE_EXIT:%.*]]
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; CHECK: guarded:
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; CHECK-NEXT: br i1 true, label [[BACKEDGE]], label [[SIDE_EXIT]]
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; CHECK: backedge:
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i32 [[IV]], 1
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; CHECK-NEXT: [[LOOP_COND:%.*]] = call i1 @cond()
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; CHECK-NEXT: br i1 [[LOOP_COND]], label [[LOOP]], label [[EXIT:%.*]]
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; CHECK: exit:
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; CHECK-NEXT: ret i32 1
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; CHECK: side_exit:
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%start = load i32, ptr %p, !range !0
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%end = load i32, ptr %s, !range !0
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br label %loop
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loop:
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%iv = phi i32 [%start, %entry], [%iv.next, %backedge]
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%c1 = icmp ult i32 %iv, %end
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br i1 %c1, label %guarded, label %side_exit
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guarded:
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%c2 = icmp slt i32 %iv, %end
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br i1 %c2, label %backedge, label %side_exit
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backedge:
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%iv.next = add nuw nsw i32 %iv, 1
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%loop.cond = call i1 @cond()
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br i1 %loop.cond, label %loop, label %exit
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exit:
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ret i32 1
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side_exit:
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ret i32 0
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}
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!0 = !{i32 -1000, i32 0}
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