3157758190
Sub-reductions can be implemented in two ways:
(1) negate the operand in the vector loop (the default way).
(2) subtract the reduced value from the init value in the middle block.
Note that both ways keep the reduction itself as an 'add' reduction,
which is necessary because only llvm.vector.partial.reduce.add exists.
The ISD nodes for partial reductions don't support folding the
sub/negation into its operands because the following is not a valid
transformation:
```
sub(0, mul(ext(a), ext(b)))
-> mul(ext(a), ext(sub(0, b)))
```
It can therefore be better to choose option (2) such that the partial
reduction is always positive (starting at '0') and to do a final
subtract in the middle block.
For AArch64 there are no dot-product instructions that can
do a `partial.reduce.sub(acc, mul(ext(a), ext(b)))` operation.
I'm not sure if such instructions exist for other targets.
(If so then we may want to make this decision a target option)
This PR also increases the AArch64 cost of a partial sub-reduction
when this exists in an 'add-sub' reduction chain.
Fixes https://github.com/llvm/llvm-project/issues/178703
85 lines
3.6 KiB
LLVM
85 lines
3.6 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -passes=loop-vectorize \
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; RUN: -scalable-vectorization=on -mattr=+sve2 \
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; RUN: -enable-epilogue-vectorization=false -debug-only=loop-vectorize \
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; RUN: -disable-output < %s 2>&1 | FileCheck %s --check-prefixes=COMMON,SVE
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; RUN: opt -passes=loop-vectorize \
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; RUN: -scalable-vectorization=off -mattr=+neon,+dotprod \
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; RUN: -enable-epilogue-vectorization=false -debug-only=loop-vectorize \
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; RUN: -disable-output < %s 2>&1 | FileCheck %s --check-prefixes=COMMON,NEON
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; COMMON: LV: Checking a loop in 'sub_reduction'
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; SVE: Cost of 1 for VF vscale x 16: EXPRESSION vp<{{.*}}> = ir<%acc> + partial.reduce.add (mul (ir<%load1> sext to i32), (ir<%load2> sext to i32))
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; NEON: Cost of 1 for VF 16: EXPRESSION vp<{{.*}}> = ir<%acc> + partial.reduce.add (mul (ir<%load1> sext to i32), (ir<%load2> sext to i32))
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; COMMON: LV: Checking a loop in 'add_sub_chained_reduction'
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; SVE: Cost of 1 for VF vscale x 16: EXPRESSION vp<{{.*}}> = ir<%acc> + partial.reduce.add (mul (ir<%load1> sext to i32), (ir<%load2> sext to i32))
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; SVE: Cost of 9 for VF vscale x 16: EXPRESSION vp<{{.*}}> = vp<%9> + partial.reduce.add (sub (0, mul (ir<%load2> sext to i32), (ir<%load3> sext to i32)))
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; NEON: Cost of 1 for VF 16: EXPRESSION vp<{{.*}}> = ir<%acc> + partial.reduce.add (mul (ir<%load1> sext to i32), (ir<%load2> sext to i32))
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; NEON: Cost of 9 for VF 16: EXPRESSION vp<{{.*}}> = vp<%9> + partial.reduce.add (sub (0, mul (ir<%load2> sext to i32), (ir<%load3> sext to i32)))
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target triple = "aarch64"
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; Test the cost of a SUB reduction, where the SUB is implemented outside the loop
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; and therefore not part of the partial reduction.
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define i32 @sub_reduction(ptr %arr1, ptr %arr2, i32 %init, i32 %n) #0 {
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%acc = phi i32 [ %init, %entry ], [ %sub, %loop ]
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%gep1 = getelementptr inbounds i8, ptr %arr1, i32 %iv
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%load1 = load i8, ptr %gep1
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%sext1 = sext i8 %load1 to i32
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%gep2 = getelementptr inbounds i8, ptr %arr2, i32 %iv
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%load2 = load i8, ptr %gep2
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%sext2 = sext i8 %load2 to i32
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%mul = mul i32 %sext1, %sext2
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%sub = sub i32 %acc, %mul
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%iv.next = add i32 %iv, 1
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%cmp = icmp ult i32 %iv.next, %n
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br i1 %cmp, label %loop, label %exit, !llvm.loop !0
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exit:
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ret i32 %sub
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}
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; Test that the cost of a SUB that is part of an ADD-SUB reduction chain
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; is high, because the negation happens inside the loop and cannot be
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; folded into the SDOT instruction (because of the extend).
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define i32 @add_sub_chained_reduction(ptr %arr1, ptr %arr2, ptr %arr3, i32 %init, i32 %n) #0 {
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entry:
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br label %loop
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loop:
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%iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ]
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%acc = phi i32 [ %init, %entry ], [ %sub, %loop ]
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%gep1 = getelementptr inbounds i8, ptr %arr1, i32 %iv
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%load1 = load i8, ptr %gep1
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%sext1 = sext i8 %load1 to i32
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%gep2 = getelementptr inbounds i8, ptr %arr2, i32 %iv
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%load2 = load i8, ptr %gep2
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%sext2 = sext i8 %load2 to i32
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%mul1 = mul i32 %sext1, %sext2
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%add = add i32 %acc, %mul1
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%gep3 = getelementptr inbounds i8, ptr %arr3, i32 %iv
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%load3 = load i8, ptr %gep3
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%sext3 = sext i8 %load3 to i32
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%mul2 = mul i32 %sext2, %sext3
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%sub = sub i32 %add, %mul2
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%iv.next = add i32 %iv, 1
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%cmp = icmp ult i32 %iv.next, %n
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br i1 %cmp, label %loop, label %exit, !llvm.loop !0
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exit:
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ret i32 %sub
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}
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attributes #0 = { vscale_range(1,16) }
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!0 = distinct !{!0, !1, !2}
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!1 = !{!"llvm.loop.interleave.count", i32 1}
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!2 = !{!"llvm.loop.vectorize.width", i32 16}
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