f8317bb256
This is a special calling convention to be used by the GHC compiler. Differential Revision: https://reviews.llvm.org/D89788
215 lines
7.5 KiB
C++
215 lines
7.5 KiB
C++
//===-- RISCVRegisterInfo.cpp - RISCV Register Information ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the RISCV implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVRegisterInfo.h"
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#include "RISCV.h"
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#include "RISCVMachineFunctionInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#define GET_REGINFO_TARGET_DESC
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#include "RISCVGenRegisterInfo.inc"
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using namespace llvm;
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static_assert(RISCV::X1 == RISCV::X0 + 1, "Register list not consecutive");
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static_assert(RISCV::X31 == RISCV::X0 + 31, "Register list not consecutive");
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static_assert(RISCV::F1_F == RISCV::F0_F + 1, "Register list not consecutive");
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static_assert(RISCV::F31_F == RISCV::F0_F + 31,
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"Register list not consecutive");
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static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
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static_assert(RISCV::F31_D == RISCV::F0_D + 31,
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"Register list not consecutive");
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static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
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static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
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RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
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: RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
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/*PC*/0, HwMode) {}
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const MCPhysReg *
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RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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auto &Subtarget = MF->getSubtarget<RISCVSubtarget>();
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if (MF->getFunction().getCallingConv() == CallingConv::GHC)
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return CSR_NoRegs_SaveList;
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if (MF->getFunction().hasFnAttribute("interrupt")) {
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if (Subtarget.hasStdExtD())
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return CSR_XLEN_F64_Interrupt_SaveList;
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if (Subtarget.hasStdExtF())
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return CSR_XLEN_F32_Interrupt_SaveList;
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return CSR_Interrupt_SaveList;
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}
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switch (Subtarget.getTargetABI()) {
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default:
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llvm_unreachable("Unrecognized ABI");
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case RISCVABI::ABI_ILP32:
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case RISCVABI::ABI_LP64:
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return CSR_ILP32_LP64_SaveList;
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case RISCVABI::ABI_ILP32F:
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case RISCVABI::ABI_LP64F:
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return CSR_ILP32F_LP64F_SaveList;
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case RISCVABI::ABI_ILP32D:
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case RISCVABI::ABI_LP64D:
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return CSR_ILP32D_LP64D_SaveList;
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}
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}
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BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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const RISCVFrameLowering *TFI = getFrameLowering(MF);
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BitVector Reserved(getNumRegs());
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// Mark any registers requested to be reserved as such
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for (size_t Reg = 0; Reg < getNumRegs(); Reg++) {
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if (MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(Reg))
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markSuperRegs(Reserved, Reg);
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}
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// Use markSuperRegs to ensure any register aliases are also reserved
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markSuperRegs(Reserved, RISCV::X0); // zero
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markSuperRegs(Reserved, RISCV::X2); // sp
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markSuperRegs(Reserved, RISCV::X3); // gp
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markSuperRegs(Reserved, RISCV::X4); // tp
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if (TFI->hasFP(MF))
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markSuperRegs(Reserved, RISCV::X8); // fp
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// Reserve the base register if we need to realign the stack and allocate
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// variable-sized objects at runtime.
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if (TFI->hasBP(MF))
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markSuperRegs(Reserved, RISCVABI::getBPReg()); // bp
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assert(checkAllSuperRegsMarked(Reserved));
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return Reserved;
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}
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bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
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MCRegister PhysReg) const {
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return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
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}
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bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
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return PhysReg == RISCV::X0;
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}
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const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
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return CSR_NoRegs_RegMask;
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}
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// Frame indexes representing locations of CSRs which are given a fixed location
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// by save/restore libcalls.
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static const std::map<unsigned, int> FixedCSRFIMap = {
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{/*ra*/ RISCV::X1, -1},
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{/*s0*/ RISCV::X8, -2},
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{/*s1*/ RISCV::X9, -3},
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{/*s2*/ RISCV::X18, -4},
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{/*s3*/ RISCV::X19, -5},
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{/*s4*/ RISCV::X20, -6},
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{/*s5*/ RISCV::X21, -7},
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{/*s6*/ RISCV::X22, -8},
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{/*s7*/ RISCV::X23, -9},
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{/*s8*/ RISCV::X24, -10},
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{/*s9*/ RISCV::X25, -11},
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{/*s10*/ RISCV::X26, -12},
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{/*s11*/ RISCV::X27, -13}
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};
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bool RISCVRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
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Register Reg,
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int &FrameIdx) const {
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const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
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if (!RVFI->useSaveRestoreLibCalls(MF))
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return false;
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auto FII = FixedCSRFIMap.find(Reg);
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if (FII == FixedCSRFIMap.end())
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return false;
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FrameIdx = FII->second;
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return true;
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}
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void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
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MachineInstr &MI = *II;
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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const RISCVInstrInfo *TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
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DebugLoc DL = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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Register FrameReg;
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int Offset = getFrameLowering(MF)
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->getFrameIndexReference(MF, FrameIndex, FrameReg)
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.getFixed() +
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MI.getOperand(FIOperandNum + 1).getImm();
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if (!isInt<32>(Offset)) {
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report_fatal_error(
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"Frame offsets outside of the signed 32-bit range not supported");
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}
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MachineBasicBlock &MBB = *MI.getParent();
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bool FrameRegIsKill = false;
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if (!isInt<12>(Offset)) {
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assert(isInt<32>(Offset) && "Int32 expected");
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// The offset won't fit in an immediate, so use a scratch register instead
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// Modify Offset and FrameReg appropriately
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Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
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TII->movImm(MBB, II, DL, ScratchReg, Offset);
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BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
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.addReg(FrameReg)
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.addReg(ScratchReg, RegState::Kill);
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Offset = 0;
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FrameReg = ScratchReg;
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FrameRegIsKill = true;
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}
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MI.getOperand(FIOperandNum)
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.ChangeToRegister(FrameReg, false, false, FrameRegIsKill);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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}
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Register RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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const TargetFrameLowering *TFI = getFrameLowering(MF);
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return TFI->hasFP(MF) ? RISCV::X8 : RISCV::X2;
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}
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const uint32_t *
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RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF,
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CallingConv::ID CC) const {
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auto &Subtarget = MF.getSubtarget<RISCVSubtarget>();
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if (CC == CallingConv::GHC)
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return CSR_NoRegs_RegMask;
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switch (Subtarget.getTargetABI()) {
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default:
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llvm_unreachable("Unrecognized ABI");
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case RISCVABI::ABI_ILP32:
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case RISCVABI::ABI_LP64:
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return CSR_ILP32_LP64_RegMask;
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case RISCVABI::ABI_ILP32F:
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case RISCVABI::ABI_LP64F:
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return CSR_ILP32F_LP64F_RegMask;
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case RISCVABI::ABI_ILP32D:
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case RISCVABI::ABI_LP64D:
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return CSR_ILP32D_LP64D_RegMask;
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}
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}
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