f8bf7d7f42
In a future patch, this will help cleanup m0 handling. The register coalescer handles copies from a register that materializes an immediate, but doesn't handle move immediates itself. The virtual register uses will often be allocated to the same register, so there end up being no real copy. llvm-svn: 374257
67 lines
3.2 KiB
LLVM
67 lines
3.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs | FileCheck -check-prefix=GCN %s
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; An assert was hit when frame offset register was used to address FrameIndex.
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define amdgpu_kernel void @kernel_background_evaluate(float addrspace(5)* %kg, <4 x i32> addrspace(1)* %input, <4 x float> addrspace(1)* %output, i32 %i) {
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; GCN-LABEL: kernel_background_evaluate:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dword s6, s[0:1], 0x24
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; GCN-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
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; GCN-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
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; GCN-NEXT: s_mov_b32 s38, -1
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; GCN-NEXT: s_mov_b32 s39, 0x31c16000
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; GCN-NEXT: s_mov_b32 s33, s3
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; GCN-NEXT: s_mov_b64 s[0:1], s[36:37]
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; GCN-NEXT: v_mov_b32_e32 v1, 0x2000
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; GCN-NEXT: v_mov_b32_e32 v2, 0x4000
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; GCN-NEXT: v_mov_b32_e32 v3, 0
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; GCN-NEXT: s_mov_b64 s[2:3], s[38:39]
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; GCN-NEXT: v_mov_b32_e32 v4, 0x400000
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; GCN-NEXT: s_add_u32 s32, s33, 0xc0000
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; GCN-NEXT: v_add_nc_u32_e64 v32, 4, 0x4000
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; GCN-NEXT: ; implicit-def: $vcc_hi
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; GCN-NEXT: s_getpc_b64 s[4:5]
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; GCN-NEXT: s_add_u32 s4, s4, svm_eval_nodes@rel32@lo+4
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; GCN-NEXT: s_addc_u32 s5, s5, svm_eval_nodes@rel32@hi+4
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: v_mov_b32_e32 v0, s6
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; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; GCN-NEXT: s_and_saveexec_b32 s0, vcc_lo
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; GCN-NEXT: ; mask branch BB0_2
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; GCN-NEXT: s_cbranch_execz BB0_2
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; GCN-NEXT: BB0_1: ; %if.then4.i
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; GCN-NEXT: buffer_load_dword v0, v32, s[36:39], s32 offen
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; GCN-NEXT: buffer_load_dword v1, v32, s[36:39], s32 offen offset:4
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; GCN-NEXT: s_waitcnt vmcnt(0)
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; GCN-NEXT: v_add_nc_u32_e32 v0, v1, v0
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; GCN-NEXT: v_mul_lo_u32 v0, 0x41c64e6d, v0
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; GCN-NEXT: v_add_nc_u32_e32 v0, 0x3039, v0
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; GCN-NEXT: buffer_store_dword v0, v0, s[36:39], s33 offen
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; GCN-NEXT: BB0_2: ; %shader_eval_surface.exit
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; GCN-NEXT: s_endpgm
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entry:
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%sd = alloca < 1339 x i32>, align 16, addrspace(5)
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%state = alloca <4 x i32>, align 4, addrspace(5)
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%rslt = call i32 @svm_eval_nodes(float addrspace(5)* %kg, <1339 x i32> addrspace(5)* %sd, <4 x i32> addrspace(5)* %state, i32 0, i32 4194304)
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%cmp = icmp eq i32 %rslt, 0
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br i1 %cmp, label %shader_eval_surface.exit, label %if.then4.i
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if.then4.i: ; preds = %entry
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%rng_hash.i.i = getelementptr inbounds < 4 x i32>, <4 x i32> addrspace(5)* %state, i32 0, i32 1
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%tmp0 = load i32, i32 addrspace(5)* %rng_hash.i.i, align 4
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%rng_offset.i.i = getelementptr inbounds <4 x i32>, <4 x i32> addrspace(5)* %state, i32 0, i32 2
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%tmp1 = load i32, i32 addrspace(5)* %rng_offset.i.i, align 4
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%add.i.i = add i32 %tmp1, %tmp0
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%add1.i.i = add i32 %add.i.i, 0
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%mul.i.i.i.i = mul i32 %add1.i.i, 1103515245
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%add.i.i.i.i = add i32 %mul.i.i.i.i, 12345
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store i32 %add.i.i.i.i, i32 addrspace(5)* undef, align 16
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br label %shader_eval_surface.exit
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shader_eval_surface.exit: ; preds = %entry
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ret void
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}
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declare hidden i32 @svm_eval_nodes(float addrspace(5)*, <1339 x i32> addrspace(5)*, <4 x i32> addrspace(5)*, i32, i32) local_unnamed_addr
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