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llvm-project/llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-fp-nosave.ll
Aaditya fbd2467796
[AMDGPU] DPP implementations for Wave Reduction (#185814) 
Adding DPP reduction support for i32 types.
Supported Ops: `umin`, `min`, `umax`, `max`,
`add`, `sub`, `and`, `or`, `xor`.
2026-03-18 13:11:53 +05:30

711 lines
29 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-wavefrontsize32,+wavefrontsize64 < %s 2>&1 | FileCheck -check-prefix=GFX12 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s 2>&1 | FileCheck -check-prefix=GFX942 %s
; These situations are "special" in that they either have an alloca that is not
; in the entry block or that they have a dynamic alloca. Both situations affect
; prolog/epilog generation.
declare amdgpu_gfx void @foo()
define amdgpu_cs_chain void @test_alloca() {
; GFX12-LABEL: test_alloca:
; GFX12: ; %bb.0: ; %.entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b32 s0, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s0, 0x400
; GFX12-NEXT: scratch_store_b32 off, v0, s0
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_alloca:
; GFX942: ; %bb.0: ; %.entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_mov_b32 s0, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_add_i32 s32, s0, 0x400
; GFX942-NEXT: scratch_store_dword off, v0, s0
; GFX942-NEXT: s_endpgm
.entry:
br label %SW_C
SW_C: ; preds = %.entry
%v = alloca i32, i32 1, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
ret void
}
define amdgpu_cs_chain void @test_alloca_chain() {
; GFX12-LABEL: test_alloca_chain:
; GFX12: ; %bb.0: ; %.entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, test_fp_all@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, test_fp_all@gotpcrel32@hi+24
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
; GFX12-NEXT: v_mov_b32_e32 v8, 57
; GFX12-NEXT: s_mov_b32 s0, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s0, 0x400
; GFX12-NEXT: scratch_store_b32 off, v0, s0
; GFX12-NEXT: s_mov_b32 s0, 51
; GFX12-NEXT: s_mov_b32 s32, s33
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b64 exec, -1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
;
; GFX942-LABEL: test_alloca_chain:
; GFX942: ; %bb.0: ; %.entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_mov_b32 s4, s32
; GFX942-NEXT: s_add_i32 s32, s4, 0x400
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, test_fp_all@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, test_fp_all@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_mov_b32 s0, 51
; GFX942-NEXT: v_mov_b32_e32 v8, 57
; GFX942-NEXT: scratch_store_dword off, v0, s4
; GFX942-NEXT: s_mov_b32 s32, s33
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_mov_b64 exec, -1
; GFX942-NEXT: s_setpc_b64 s[2:3]
.entry:
br label %SW_C
SW_C: ; preds = %.entry
%v = alloca i32, i32 1, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
call void(ptr, i64, i32, i32, i32, ...) @llvm.amdgcn.cs.chain.i32(ptr @test_fp_all, i64 -1, i32 inreg 51, i32 57, i32 0)
unreachable
}
define amdgpu_cs_chain void @test_alloca_var_uniform(i32 inreg %count) {
; GFX12-LABEL: test_alloca_var_uniform:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: s_mov_b32 s1, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_lshl_b32 s0, s0, 6
; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s1, s0
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_alloca_var_uniform:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_and_b32 s0, s0, -16
; GFX942-NEXT: s_lshl_b32 s0, s0, 6
; GFX942-NEXT: s_mov_b32 s1, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_add_i32 s32, s1, s0
; GFX942-NEXT: scratch_store_dword off, v0, s1
; GFX942-NEXT: s_endpgm
%v = alloca i32, i32 %count, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
ret void
}
define amdgpu_cs_chain void @test_alloca_var(i32 %count) {
; GFX12-LABEL: test_alloca_var:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_lshl_add_u32 v3, v8, 2, 15
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_and_b32_e32 v3, -16, v3
; GFX12-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, v3, s[0:1]
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_mbcnt_hi_u32_b32 v2, -1, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_add_nc_u32_e32 v2, 32, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_mul_lo_u32 v2, 4, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: ds_swizzle_b32 v1, v0 offset:swizzle(BROADCAST,32,15)
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-NEXT: ds_permute_b32 v1, v2, v0
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s2, v0, 63
; GFX12-NEXT: s_mov_b64 exec, s[0:1]
; GFX12-NEXT: s_mov_b32 s0, s32
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshl_add_u32 v3, s2, 6, s0
; GFX12-NEXT: scratch_store_b32 off, v4, s0
; GFX12-NEXT: v_readfirstlane_b32 s32, v3
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_alloca_var:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_lshl_add_u32 v1, v8, 2, 15
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: v_and_b32_e32 v1, -16, v1
; GFX942-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readlane_b32 s2, v0, 63
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: s_mov_b32 s0, s32
; GFX942-NEXT: v_mov_b32_e32 v1, s0
; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s32, v1
; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: scratch_store_dword off, v1, s0
; GFX942-NEXT: s_endpgm
%v = alloca i32, i32 %count, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
ret void
}
define amdgpu_cs_chain void @test_alloca_and_call() {
; GFX12-LABEL: test_alloca_and_call:
; GFX12: ; %bb.0: ; %.entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, foo@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo@gotpcrel32@hi+24
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: s_mov_b32 s2, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s2, 0x400
; GFX12-NEXT: scratch_store_b32 off, v0, s2
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_alloca_and_call:
; GFX942: ; %bb.0: ; %.entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s2, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_add_i32 s32, s2, 0x400
; GFX942-NEXT: scratch_store_dword off, v0, s2
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: s_endpgm
.entry:
br label %SW_C
SW_C: ; preds = %.entry
%v = alloca i32, i32 1, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
call amdgpu_gfx void @foo()
ret void
}
define amdgpu_cs_chain void @test_alloca_and_call_var_uniform(i32 inreg %count) {
; GFX12-LABEL: test_alloca_and_call_var_uniform:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24
; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: s_mov_b32 s1, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_lshl_b32 s0, s0, 6
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s1, s0
; GFX12-NEXT: scratch_store_b32 off, v0, s1
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_alloca_and_call_var_uniform:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX942-NEXT: s_and_b32 s0, s0, -16
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_lshl_b32 s2, s0, 6
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s3, s32
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: s_add_i32 s32, s3, s2
; GFX942-NEXT: scratch_store_dword off, v0, s3
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: s_endpgm
%v = alloca i32, i32 %count, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
call amdgpu_gfx void @foo()
ret void
}
define amdgpu_cs_chain void @test_alloca_and_call_var(i32 %count) {
; GFX12-LABEL: test_alloca_and_call_var:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_lshl_add_u32 v3, v8, 2, 15
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_and_b32_e32 v3, -16, v3
; GFX12-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, v3, s[0:1]
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 0
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_mbcnt_hi_u32_b32 v2, -1, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_add_nc_u32_e32 v2, 32, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_mul_lo_u32 v2, 4, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: ds_swizzle_b32 v1, v0 offset:swizzle(BROADCAST,32,15)
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-NEXT: ds_permute_b32 v1, v2, v0
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-NEXT: s_mov_b64 exec, s[0:1]
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX12-NEXT: s_or_saveexec_b64 s[2:3], -1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s4, v0, 63
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b64 exec, s[2:3]
; GFX12-NEXT: s_mov_b32 s2, s32
; GFX12-NEXT: v_mov_b32_e32 v4, 0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshl_add_u32 v3, s4, 6, s2
; GFX12-NEXT: scratch_store_b32 off, v4, s2
; GFX12-NEXT: v_readfirstlane_b32 s32, v3
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_alloca_and_call_var:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_lshl_add_u32 v1, v8, 2, 15
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: v_and_b32_e32 v1, -16, v1
; GFX942-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readlane_b32 s2, v0, 63
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s3, s32
; GFX942-NEXT: v_mov_b32_e32 v1, s3
; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s32, v1
; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: scratch_store_dword off, v1, s3
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: s_endpgm
%v = alloca i32, i32 %count, align 4, addrspace(5)
store i32 0, ptr addrspace(5) %v, align 4
call amdgpu_gfx void @foo()
ret void
}
define amdgpu_cs_chain void @test_call_and_alloca() {
; GFX12-LABEL: test_call_and_alloca:
; GFX12: ; %bb.0: ; %.entry
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, foo@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, foo@gotpcrel32@hi+24
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: s_add_co_i32 s32, s4, 0x400
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: scratch_store_b32 off, v0, s4
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_call_and_alloca:
; GFX942: ; %bb.0: ; %.entry
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s4, s32
; GFX942-NEXT: s_add_i32 s32, s4, 0x400
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: scratch_store_dword off, v0, s4
; GFX942-NEXT: s_endpgm
.entry:
br label %SW_C
SW_C: ; preds = %.entry
%v = alloca i32, i32 1, align 4, addrspace(5)
call amdgpu_gfx void @foo()
store i32 0, ptr addrspace(5) %v, align 4
ret void
}
define amdgpu_cs_chain void @test_call_and_alloca_var_uniform(i32 inreg %count) {
; GFX12-LABEL: test_call_and_alloca_var_uniform:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24
; GFX12-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX12-NEXT: s_load_b64 s[2:3], s[2:3], 0x0
; GFX12-NEXT: s_and_b32 s0, s0, -16
; GFX12-NEXT: s_mov_b32 s4, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_lshl_b32 s0, s0, 6
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_i32 s32, s4, s0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[2:3]
; GFX12-NEXT: v_mov_b32_e32 v0, 0
; GFX12-NEXT: scratch_store_b32 off, v0, s4
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_call_and_alloca_var_uniform:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_lshl2_add_u32 s0, s0, 15
; GFX942-NEXT: s_and_b32 s0, s0, -16
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: s_lshl_b32 s2, s0, 6
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s4, s32
; GFX942-NEXT: s_add_i32 s32, s4, s2
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: v_mov_b32_e32 v0, 0
; GFX942-NEXT: scratch_store_dword off, v0, s4
; GFX942-NEXT: s_endpgm
%v = alloca i32, i32 %count, align 4, addrspace(5)
call amdgpu_gfx void @foo()
store i32 0, ptr addrspace(5) %v, align 4
ret void
}
define amdgpu_cs_chain void @test_call_and_alloca_var(i32 %count) {
; GFX12-LABEL: test_call_and_alloca_var:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: v_lshl_add_u32 v3, v8, 2, 15
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_add_co_i32 s32, s32, 16
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_and_b32_e32 v3, -16, v3
; GFX12-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, v3, s[0:1]
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 0
; GFX12-NEXT: s_getpc_b64 s[2:3]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s3, s3
; GFX12-NEXT: s_add_co_u32 s2, s2, foo@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s3, s3, foo@gotpcrel32@hi+24
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_mbcnt_hi_u32_b32 v2, -1, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_add_nc_u32_e32 v2, 32, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: v_mul_lo_u32 v2, 4, v2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX12-NEXT: ds_swizzle_b32 v1, v0 offset:swizzle(BROADCAST,32,15)
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-NEXT: ds_permute_b32 v1, v2, v0
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_max_u32_e32 v0, v0, v1
; GFX12-NEXT: s_mov_b64 exec, s[0:1]
; GFX12-NEXT: s_load_b64 s[0:1], s[2:3], 0x0
; GFX12-NEXT: s_or_saveexec_b64 s[2:3], -1
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readlane_b32 s4, v0, 63
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_mov_b64 exec, s[2:3]
; GFX12-NEXT: s_mov_b32 s5, s32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshl_add_u32 v3, s4, 6, s5
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_readfirstlane_b32 s32, v3
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX12-NEXT: v_mov_b32_e32 v3, 0
; GFX12-NEXT: scratch_store_b32 off, v3, s5
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_call_and_alloca_var:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: v_lshl_add_u32 v1, v8, 2, 15
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_add_i32 s32, s32, 16
; GFX942-NEXT: v_and_b32_e32 v1, -16, v1
; GFX942-NEXT: s_or_saveexec_b64 s[0:1], -1
; GFX942-NEXT: v_cndmask_b32_e64 v0, 0, v1, s[0:1]
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:1 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:2 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:4 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_shr:8 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 1
; GFX942-NEXT: v_max_u32_dpp v0, v0, v0 row_bcast:31 row_mask:0xf bank_mask:0xf
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readlane_b32 s2, v0, 63
; GFX942-NEXT: s_mov_b64 exec, s[0:1]
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s4, s32
; GFX942-NEXT: v_mov_b32_e32 v1, s4
; GFX942-NEXT: v_lshl_add_u32 v1, s2, 6, v1
; GFX942-NEXT: s_nop 0
; GFX942-NEXT: v_readfirstlane_b32 s32, v1
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_swappc_b64 s[30:31], s[0:1]
; GFX942-NEXT: v_mov_b32_e32 v1, 0
; GFX942-NEXT: scratch_store_dword off, v1, s4
; GFX942-NEXT: s_endpgm
%v = alloca i32, i32 %count, align 4, addrspace(5)
call amdgpu_gfx void @foo()
store i32 0, ptr addrspace(5) %v, align 4
ret void
}
define amdgpu_cs_chain void @test_fp_all() #0 {
; GFX12-LABEL: test_fp_all:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_endpgm
;
; GFX942-LABEL: test_fp_all:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_endpgm
ret void
}
define amdgpu_cs_chain void @test_fp_all_chain() #0 {
; GFX12-LABEL: test_fp_all_chain:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT: s_wait_expcnt 0x0
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_getpc_b64 s[0:1]
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_sext_i32_i16 s1, s1
; GFX12-NEXT: s_add_co_u32 s0, s0, test_fp_all@gotpcrel32@lo+12
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_add_co_ci_u32 s1, s1, test_fp_all@gotpcrel32@hi+24
; GFX12-NEXT: v_mov_b32_e32 v8, 57
; GFX12-NEXT: s_load_b64 s[2:3], s[0:1], 0x0
; GFX12-NEXT: s_mov_b32 s0, 51
; GFX12-NEXT: s_mov_b32 s33, s32
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_mov_b64 exec, -1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_setpc_b64 s[2:3]
;
; GFX942-LABEL: test_fp_all_chain:
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_getpc_b64 s[0:1]
; GFX942-NEXT: s_add_u32 s0, s0, test_fp_all@gotpcrel32@lo+4
; GFX942-NEXT: s_addc_u32 s1, s1, test_fp_all@gotpcrel32@hi+12
; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0
; GFX942-NEXT: s_mov_b32 s0, 51
; GFX942-NEXT: v_mov_b32_e32 v8, 57
; GFX942-NEXT: s_mov_b32 s33, s32
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
; GFX942-NEXT: s_mov_b64 exec, -1
; GFX942-NEXT: s_setpc_b64 s[2:3]
call void(ptr, i64, i32, i32, i32, ...) @llvm.amdgcn.cs.chain.i32(ptr @test_fp_all, i64 -1, i32 inreg 51, i32 57, i32 0)
unreachable
}
declare void @llvm.amdgcn.cs.chain.i32(ptr, i64, i32, i32, i32, ...)
attributes #0 = { "frame-pointer"="all" }
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