49d5bb0ad0
This PR introduces `amdgpu-lower-exec-sync` pass which specifically lowers named-barrier LDS globals introduced by #114550 . Changes include: - Moving the logic of lowering named-barrier LDS globals from `amdgpu-lower-module-lds` pass to this new pass. - This PR adds the pass to pipeline, remove the existing lowering logic for named-barrier LDS in `amdgpu-lower-module-lds` See #161827 for discussion on this topic.
74 lines
3.5 KiB
LLVM
74 lines
3.5 KiB
LLVM
; RUN: opt -S -mtriple=amdgcn-- -passes=amdgpu-lower-exec-sync,amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false < %s 2>&1 | FileCheck %s
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; RUN: llc < %s -enable-new-pm -stop-after=amdgpu-sw-lower-lds -amdgpu-asan-instrument-lds=false -mtriple=amdgcn-amd-amdhsa | FileCheck %s
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; Test to ensure that LDS variables like named barriers are lowered correctly in asan scenario,
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; where amdgpu-sw-lower-lds pass runs in pipeline after amdgpu-lower-exec-sync pass.
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%class.ExpAmdWorkgroupWaveBarrier = type { target("amdgcn.named.barrier", 0) }
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@bar2 = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison
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@bar1 = internal addrspace(3) global [4 x %class.ExpAmdWorkgroupWaveBarrier] poison
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@lds1 = internal addrspace(3) global [1 x i8] poison, align 4
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;.
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; CHECK: @bar2 = internal addrspace(3) global [2 x target("amdgcn.named.barrier", 0)] poison, !absolute_symbol [[META0:![0-9]+]]
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; CHECK: @bar1 = internal addrspace(3) global [4 x %class.ExpAmdWorkgroupWaveBarrier] poison, !absolute_symbol [[META1:![0-9]+]]
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;
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define void @bar() #0 {
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; CHECK-LABEL: define void @bar(
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; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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; CHECK: call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar2, i32 7)
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; CHECK: call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar2)
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; CHECK: call void @llvm.amdgcn.s.barrier.wait(i16 1)
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; CHECK: store i8 7, ptr addrspace(1) {{.*}}, align 4
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;
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call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar2, i32 7)
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call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar2)
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call void @llvm.amdgcn.s.barrier.wait(i16 1)
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store i8 7, ptr addrspace(3) @lds1, align 4
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ret void
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}
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define amdgpu_kernel void @barkernel() #0 {
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; CHECK-LABEL: define amdgpu_kernel void @barkernel(
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; CHECK-SAME: ) #[[ATTR1:[0-9]+]] !llvm.amdgcn.lds.kernel.id [[META4:![0-9]+]] {
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; CHECK: {{.*}} = call i64 @__asan_malloc_impl(i64 {{.*}}, i64 {{.*}})
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; CHECK: call void @llvm.amdgcn.s.barrier()
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; CHECK: call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar1, i32 9)
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; CHECK: call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar1)
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; CHECK: call void @llvm.amdgcn.s.barrier.wait(i16 1)
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; CHECK: call void @bar()
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; CHECK: store i8 10, ptr addrspace(1) {{.*}}, align 4
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; CHECK: call void @__asan_free_impl(i64 {{.*}}, i64 {{.*}})
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;
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call void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3) @bar1, i32 9)
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call void @llvm.amdgcn.s.barrier.join(ptr addrspace(3) @bar1)
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call void @llvm.amdgcn.s.barrier.wait(i16 1)
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call void @bar()
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store i8 10, ptr addrspace(3) @lds1, align 4
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ret void
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}
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declare void @llvm.amdgcn.s.barrier() #1
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declare void @llvm.amdgcn.s.barrier.wait(i16) #1
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declare void @llvm.amdgcn.s.barrier.signal(i32) #1
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declare void @llvm.amdgcn.s.barrier.signal.var(ptr addrspace(3), i32) #1
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declare i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32) #1
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declare void @llvm.amdgcn.s.barrier.init(ptr addrspace(3), i32) #1
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declare void @llvm.amdgcn.s.barrier.join(ptr addrspace(3)) #1
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declare void @llvm.amdgcn.s.barrier.leave(i16) #1
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declare void @llvm.amdgcn.s.wakeup.barrier(ptr addrspace(3)) #1
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declare i32 @llvm.amdgcn.s.get.named.barrier.state(ptr addrspace(3)) #1
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attributes #0 = { nounwind sanitize_address }
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attributes #1 = { convergent nounwind }
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attributes #2 = { nounwind readnone }
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!llvm.module.flags = !{!0}
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!0 = !{i32 4, !"nosanitize_address", i32 1}
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;.
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; CHECK: attributes #[[ATTR0]] = { nounwind sanitize_address }
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; CHECK: attributes #[[ATTR1]] = { nounwind sanitize_address "amdgpu-lds-size"="8" }
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;.
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; CHECK: [[META0]] = !{i32 8396880, i32 8396881}
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; CHECK: [[META1]] = !{i32 8396816, i32 8396817}
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;.
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