5138b61a25
Some of the packed build_vector use vgpr_32 for i16/f16/bf16. In gfx11, bf16 arithmetic get promoted to f32 and this is done via v2i16 pack. In true16 mode this v2i16 pack is selected to a build_vector/v_lshlrev pattern which only accepts VGPR32. This causes isel to insert an illegal copy "vgpr32 = copy vgpr16" between def and use. In the end this illegal copy confuses cse pass and trigger wrong code elimination. Remove the packed build_vector pattern from true16. After removal, ISel will use vgpr16 build_vector patterns instead.
123 lines
6.4 KiB
LLVM
123 lines
6.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11-TRUE16 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11-FAKE16 %s
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@global_smem = external local_unnamed_addr addrspace(1) global [0 x i8], align 16
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define amdgpu_kernel void @v_atomicrmw_fadd_bf16(ptr addrspace(1) %out, i1 %in, ptr addrspace(1) %ptr) #0 {
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; GFX11-TRUE16-LABEL: v_atomicrmw_fadd_bf16:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: s_clause 0x1
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; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
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; GFX11-TRUE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
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; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x3ff, v0
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, 0
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; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, 0
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; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-TRUE16-NEXT: global_load_b32 v2, v0, s[0:1] offset:4
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; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, -4
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; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3
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; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 3
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; GFX11-TRUE16-NEXT: s_load_b32 s3, s[0:1], 0x0
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; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 3
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
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; GFX11-TRUE16-NEXT: s_lshl_b32 s4, 0xffff, s2
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; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s3
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; GFX11-TRUE16-NEXT: s_not_b32 s3, s4
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; GFX11-TRUE16-NEXT: s_mov_b32 s4, 0
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; GFX11-TRUE16-NEXT: .p2align 6
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; GFX11-TRUE16-NEXT: .LBB0_1: ; %atomicrmw.start
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; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
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; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
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; GFX11-TRUE16-NEXT: v_bfe_u32 v5, v0, 16, 1
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; GFX11-TRUE16-NEXT: v_or_b32_e32 v6, 0x400000, v0
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; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_add3_u32 v5, v5, v0, 0x7fff
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; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc_lo
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
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; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, s2, v3
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-TRUE16-NEXT: v_and_or_b32 v0, v1, s3, v0
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; GFX11-TRUE16-NEXT: global_atomic_cmpswap_b32 v0, v4, v[0:1], s[0:1] glc
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; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-TRUE16-NEXT: buffer_gl1_inv
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; GFX11-TRUE16-NEXT: buffer_gl0_inv
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; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
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; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v0
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; GFX11-TRUE16-NEXT: s_or_b32 s4, vcc_lo, s4
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; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-TRUE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; GFX11-TRUE16-NEXT: s_cbranch_execnz .LBB0_1
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; GFX11-TRUE16-NEXT: ; %bb.2: ; %atomicrmw.end
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; GFX11-TRUE16-NEXT: s_endpgm
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;
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; GFX11-FAKE16-LABEL: v_atomicrmw_fadd_bf16:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: s_clause 0x1
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; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
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; GFX11-FAKE16-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
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; GFX11-FAKE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
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; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-FAKE16-NEXT: global_load_b32 v0, v0, s[0:1] offset:4
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; GFX11-FAKE16-NEXT: s_and_b32 s0, s2, -4
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; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3
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; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 3
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; GFX11-FAKE16-NEXT: s_load_b32 s3, s[0:1], 0x0
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; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 3
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-FAKE16-NEXT: s_lshl_b32 s4, 0xffff, s2
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; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, s3
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; GFX11-FAKE16-NEXT: s_not_b32 s3, s4
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; GFX11-FAKE16-NEXT: s_mov_b32 s4, 0
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
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; GFX11-FAKE16-NEXT: .p2align 6
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; GFX11-FAKE16-NEXT: .LBB0_1: ; %atomicrmw.start
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; GFX11-FAKE16-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, s2, v1
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; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, v0, v2
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; GFX11-FAKE16-NEXT: v_bfe_u32 v4, v0, 16, 1
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; GFX11-FAKE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
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; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_add3_u32 v4, v4, v0, 0x7fff
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; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc_lo
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
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; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, s2, v0
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-FAKE16-NEXT: v_and_or_b32 v0, v1, s3, v0
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; GFX11-FAKE16-NEXT: global_atomic_cmpswap_b32 v0, v3, v[0:1], s[0:1] glc
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; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GFX11-FAKE16-NEXT: buffer_gl1_inv
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; GFX11-FAKE16-NEXT: buffer_gl0_inv
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; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v0, v1
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; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, v0
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; GFX11-FAKE16-NEXT: s_or_b32 s4, vcc_lo, s4
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; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-FAKE16-NEXT: s_and_not1_b32 exec_lo, exec_lo, s4
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; GFX11-FAKE16-NEXT: s_cbranch_execnz .LBB0_1
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; GFX11-FAKE16-NEXT: ; %bb.2: ; %atomicrmw.end
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; GFX11-FAKE16-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr <{ [0 x i8] }>, ptr addrspace(1) %ptr, i64 0, i32 0, i32 %tid
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%load = load <4 x bfloat>, ptr addrspace(1) %in.gep
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%extract1 = extractelement <4 x bfloat> %load, i64 3
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%fadd = atomicrmw fadd ptr addrspace(1) %out, bfloat %extract1 syncscope("agent") acq_rel
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ret void
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}
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