bbde792786
Allow widening up to 128-bit registers or if the new register class is at least as large as one of the existing register classes. This was artificially limiting. In particular this was doing the wrong thing with sequences involving copies between VGPRs and AV registers. Nearly all test changes are improvements. The coalescer does not just widen registers out of nowhere. If it's trying to "widen" a register, it's generally packing a register into an existing register tuple, or in a situation where the constraints imply the wider class anyway. 067a11015 addressed the allocation failure concern by rejecting coalescing if there are no available registers. The original change in a4e63ead4b didn't include a realistic testcase to judge if this is harmful for pressure. I would expect any issues from this to be of garden variety subreg handling issue. We could use more dynamic state information here if it really is an issue. I get the best results by removing this override completely. This is a smaller step for patch splitting purposes.
167 lines
5.5 KiB
LLVM
167 lines
5.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s
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define i32 @mullohi_u32(i32 %arg, i32 %arg1, ptr %arg2) {
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; CHECK-LABEL: mullohi_u32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 0
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; CHECK-NEXT: flat_store_dword v[2:3], v1
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext i32 %arg to i64
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%i3 = zext i32 %arg1 to i64
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%i4 = mul nuw i64 %i3, %i
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%i5 = lshr i64 %i4, 32
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%i6 = trunc i64 %i5 to i32
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store i32 %i6, ptr %arg2, align 4
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%i7 = trunc i64 %i4 to i32
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ret i32 %i7
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}
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define i32 @mullohi_s32(i32 %arg, i32 %arg1, ptr %arg2) {
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; CHECK-LABEL: mullohi_s32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mad_i64_i32 v[0:1], s[4:5], v1, v0, 0
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; CHECK-NEXT: flat_store_dword v[2:3], v1
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = sext i32 %arg to i64
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%i3 = sext i32 %arg1 to i64
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%i4 = mul nsw i64 %i3, %i
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%i5 = ashr i64 %i4, 32
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%i6 = trunc i64 %i5 to i32
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store i32 %i6, ptr %arg2, align 4
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%i7 = trunc i64 %i4 to i32
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ret i32 %i7
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}
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define i32 @mullohi_u32_non_const_shift(i32 %arg, i32 %arg1, ptr %arg2, i64 %shift) {
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; CHECK-LABEL: mullohi_u32_non_const_shift:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mad_u64_u32 v[5:6], s[4:5], v1, v0, 0
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; CHECK-NEXT: v_lshrrev_b64 v[0:1], v4, v[5:6]
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; CHECK-NEXT: flat_store_dword v[2:3], v6
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext i32 %arg to i64
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%i3 = zext i32 %arg1 to i64
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%i4 = mul nuw i64 %i3, %i
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%i5 = lshr i64 %i4, 32
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%i6 = trunc i64 %i5 to i32
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store i32 %i6, ptr %arg2, align 4
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%i7 = lshr i64 %i4, %shift
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%i8 = trunc i64 %i7 to i32
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ret i32 %i8
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}
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define <2 x i32> @mullohi_2xu32(<2 x i32> %arg, <2 x i32> %arg1, ptr %arg2) {
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; CHECK-LABEL: mullohi_2xu32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mad_u64_u32 v[6:7], s[4:5], v3, v1, 0
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; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0
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; CHECK-NEXT: v_mov_b32_e32 v2, v7
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; CHECK-NEXT: flat_store_dwordx2 v[4:5], v[1:2]
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; CHECK-NEXT: v_mov_b32_e32 v1, v6
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext <2 x i32> %arg to <2 x i64>
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%i3 = zext <2 x i32> %arg1 to <2 x i64>
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%i4 = mul nuw <2 x i64> %i3, %i
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%i5 = lshr <2 x i64> %i4, <i64 32, i64 32>
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%i6 = trunc <2 x i64> %i5 to <2 x i32>
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store <2 x i32> %i6, ptr %arg2, align 8
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%i7 = trunc <2 x i64> %i4 to <2 x i32>
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ret <2 x i32> %i7
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}
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define i8 @mullohi_illegal_ty(i8 %arg, i8 %arg1, ptr %arg2) {
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; CHECK-LABEL: mullohi_illegal_ty:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_lo_u16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
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; CHECK-NEXT: v_lshrrev_b16_e32 v1, 8, v0
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; CHECK-NEXT: flat_store_byte v[2:3], v1
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext i8 %arg to i16
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%i3 = zext i8 %arg1 to i16
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%i4 = mul nuw i16 %i3, %i
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%i5 = lshr i16 %i4, 8
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%i6 = trunc i16 %i5 to i8
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store i8 %i6, ptr %arg2, align 1
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%i7 = trunc i16 %i4 to i8
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ret i8 %i7
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}
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define i32 @mul_one_bit_low_hi_u32(i32 %arg, i32 %arg1, ptr %arg2) {
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; CHECK-LABEL: mul_one_bit_low_hi_u32:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v1, v0, 0
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; CHECK-NEXT: v_alignbit_b32 v0, v1, v0, 31
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; CHECK-NEXT: flat_store_dword v[2:3], v1
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext i32 %arg to i64
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%i3 = zext i32 %arg1 to i64
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%i4 = mul nsw i64 %i3, %i
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%i5 = lshr i64 %i4, 32
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%i6 = trunc i64 %i5 to i32
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store i32 %i6, ptr %arg2, align 4
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%i7 = lshr i64 %i4, 31
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%i8 = trunc i64 %i7 to i32
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ret i32 %i8
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}
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define i32 @mul_one_bit_hi_hi_u32_lshr_lshr(i32 %arg, i32 %arg1, ptr %arg2) {
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; CHECK-LABEL: mul_one_bit_hi_hi_u32_lshr_lshr:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_hi_u32 v0, v1, v0
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; CHECK-NEXT: flat_store_dword v[2:3], v0
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; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext i32 %arg to i64
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%i3 = zext i32 %arg1 to i64
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%i4 = mul nsw i64 %i3, %i
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%i5 = lshr i64 %i4, 32
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%i6 = trunc i64 %i5 to i32
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store i32 %i6, ptr %arg2, align 4
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%i7 = lshr i64 %i4, 33
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%i8 = trunc i64 %i7 to i32
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ret i32 %i8
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}
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define i32 @mul_one_bit_hi_hi_u32_lshr_ashr(i32 %arg, i32 %arg1, ptr %arg2) {
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; CHECK-LABEL: mul_one_bit_hi_hi_u32_lshr_ashr:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: v_mul_hi_u32 v0, v1, v0
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; CHECK-NEXT: flat_store_dword v[2:3], v0
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; CHECK-NEXT: v_ashrrev_i32_e32 v0, 1, v0
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; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = zext i32 %arg to i64
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%i3 = zext i32 %arg1 to i64
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%i4 = mul nsw i64 %i3, %i
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%i5 = lshr i64 %i4, 32
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%i6 = trunc i64 %i5 to i32
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store i32 %i6, ptr %arg2, align 4
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%i7 = ashr i64 %i4, 33
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%i8 = trunc i64 %i7 to i32
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ret i32 %i8
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}
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