e95f6fa123
Introduce a target hook to incrementally flip the behavior of targets with test changes, and start by implementing it for AMDGPU. This appears to be forgotten switch flip from 2015. This seems to do a nicer job with subregister copies. Most of the test changes are improvements or neutral, not that many are light regressions. The worst AMDGPU regressions are for true16 in the atomic tests, but I think that's due to existing true16 issues.
92 lines
3.3 KiB
LLVM
92 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope --check-prefixes=GCN %s
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define amdgpu_kernel void @uniform_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: uniform_sext_in_reg_i8_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_add_i32 s2, s4, s5
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; GCN-NEXT: s_sext_i32_i8 s4, s2
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%c = add i32 %a, %b ; add to prevent folding into extload
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%shl = shl i32 %c, 24
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%ashr = ashr i32 %shl, 24
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @divergent_sext_in_reg_i8_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: divergent_sext_in_reg_i8_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_add_i32 s4, s4, s5
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 8
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%c = add i32 %a, %b ; add to prevent folding into extload
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%c.divergent = add i32 %c, %tid
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%shl = shl i32 %c.divergent, 24
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%ashr = ashr i32 %shl, 24
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @uniform_sext_in_reg_i16_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: uniform_sext_in_reg_i16_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_add_i32 s2, s4, s5
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; GCN-NEXT: s_sext_i32_i16 s4, s2
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, s4
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%c = add i32 %a, %b ; add to prevent folding into extload
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%shl = shl i32 %c, 16
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%ashr = ashr i32 %shl, 16
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_kernel void @divergent_sext_in_reg_i16_to_i32(ptr addrspace(1) %out, i32 %a, i32 %b) #0 {
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; GCN-LABEL: divergent_sext_in_reg_i16_to_i32:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: s_add_i32 s4, s4, s5
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; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v0
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; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%c = add i32 %a, %b ; add to prevent folding into extload
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%c.divergent = add i32 %c, %tid
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%shl = shl i32 %c.divergent, 16
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%ashr = ashr i32 %shl, 16
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store i32 %ashr, ptr addrspace(1) %out, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone speculatable }
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