d226f1b161
Regenerate checks after two recent commits that caused extra stuff to be added at the end of assembly lines, so the existing checks did not fail. - #179414 added "nv" to loads and stores on GFX1250. - #185774 added "msbs" comments on setreg instructions.
53 lines
2.2 KiB
LLVM
53 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN %s
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; The first load produces address in a VGPR which is used in address calculation
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; of the second load (one inside the loop). The value is uniform and the inner
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; load correctly selected to use SADDR form, however the address is promoted to
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; vector registers because it all starts with a VGPR produced by the entry block
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; load.
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;
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; Check that we are changing SADDR form of a load to VADDR and do not have to use
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; readfirstlane instructions to move address from VGPRs into SGPRs.
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define amdgpu_kernel void @test_move_load_address_to_vgpr(ptr addrspace(1) nocapture %arg1, ptr nocapture %arg2) {
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; GCN-LABEL: test_move_load_address_to_vgpr:
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; GCN: ; %bb.0: ; %bb
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: s_load_b128 s[0:3], s[4:5], 0x24 nv
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; GCN-NEXT: v_mov_b32_e32 v3, 0
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; GCN-NEXT: s_wait_kmcnt 0x0
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; GCN-NEXT: global_load_b32 v2, v3, s[0:1] scope:SCOPE_SYS
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[2:3]
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; GCN-NEXT: v_add_nc_u32_e32 v2, 0xffffff00, v2
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; GCN-NEXT: s_delay_alu instid0(VALU_DEP_2)
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; GCN-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1]
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; GCN-NEXT: .LBB0_1: ; %bb3
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_wait_dscnt 0x0
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; GCN-NEXT: flat_load_b32 v3, v[0:1] scope:SCOPE_SYS
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; GCN-NEXT: s_wait_loadcnt 0x0
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; GCN-NEXT: v_add_nc_u64_e32 v[0:1], 4, v[0:1]
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; GCN-NEXT: v_add_co_u32 v2, s0, v2, 1
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; GCN-NEXT: s_and_b32 vcc_lo, exec_lo, s0
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; GCN-NEXT: s_cbranch_vccz .LBB0_1
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; GCN-NEXT: ; %bb.2: ; %bb2
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; GCN-NEXT: s_endpgm
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bb:
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%i2 = load volatile i32, ptr addrspace(1) %arg1, align 4
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br label %bb3
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bb2: ; preds = %bb3
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ret void
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bb3: ; preds = %bb3, %bb
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%i = phi i32 [ %i2, %bb ], [ %i8, %bb3 ]
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%i4 = zext i32 %i to i64
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%i5 = getelementptr inbounds i32, ptr %arg2, i64 %i4
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%i6 = load volatile i32, ptr %i5, align 4
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%i8 = add nuw nsw i32 %i, 1
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%i9 = icmp eq i32 %i8, 256
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br i1 %i9, label %bb2, label %bb3
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}
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