80064b6e32
This helps avoid some regressions in a future patch. The or 0 pattern appears in the division tests because the reduce 64-bit bit operation to a 32-bit one with half identity value is only implemented for constants. We could fix that by using computeKnownBits. Additionally the pattern disappears if I optimize the IR division expansion, so that IR should probably be emitted more optimally in the first place.
18 lines
898 B
YAML
18 lines
898 B
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1101 -run-pass si-fold-operands %s -o - | FileCheck %s
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---
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name: test_tryFoldZeroHighBits_skips_nonreg
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tracksRegLiveness: true
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body: |
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bb.0:
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; CHECK-LABEL: name: test_tryFoldZeroHighBits_skips_nonreg
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; CHECK: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
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; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; CHECK-NEXT: S_NOP 0, implicit [[V_MOV_B32_e32_1]]
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%0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%1:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
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%2:vgpr_32 = V_AND_B32_e64 65535, %1.sub0, implicit $exec
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S_NOP 0, implicit %2
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...
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