a9c8e94b43
This patch updates the FP-to-Int conversion handling: - For signed integers: use `ftrunc` followed by clamping to the target integer range. - For unsigned integers: apply `fabs` + `ftrunc`, then clamp. This removes the previous dependence on `nsz` and ensures correct lowering for both signed and unsigned cases. I've tested the code generation of -mtriple=amdgcn. It seems that the assembly code is expected, but I'm not sure how to write a general testcase for every target. Fixes #160623.
297 lines
10 KiB
LLVM
297 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck -check-prefix=GFX6 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
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define amdgpu_kernel void @fptoui_f32_to_i16_to_f32(ptr addrspace(1) %out, float %x) {
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; GFX6-LABEL: fptoui_f32_to_i16_to_f32:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_trunc_f32_e64 v0, |s6|
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f32_to_i16_to_f32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f32_e64 v1, |s2|
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; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui float %x to i16
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%fp = uitofp i16 %ui to float
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store float %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f32_to_i32_to_f32(ptr addrspace(1) %out, float %x) {
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; GFX6-LABEL: fptoui_f32_to_i32_to_f32:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_trunc_f32_e64 v0, |s6|
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f32_to_i32_to_f32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f32_e64 v1, |s2|
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; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui float %x to i32
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%fp = uitofp i32 %ui to float
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store float %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f32_to_i64_to_f32(ptr addrspace(1) %out, float %x) {
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; GFX6-LABEL: fptoui_f32_to_i64_to_f32:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dword s6, s[4:5], 0xb
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_trunc_f32_e64 v0, |s6|
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; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f32_to_i64_to_f32:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f32_e64 v1, |s2|
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; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui float %x to i64
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%fp = uitofp i64 %ui to float
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store float %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f16_to_i16_to_f16(ptr addrspace(1) %out, half %x) {
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; GFX6-LABEL: fptoui_f16_to_i16_to_f16:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_cvt_f32_f16_e32 v0, s0
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX6-NEXT: v_cvt_u32_f32_e32 v0, v0
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; GFX6-NEXT: v_cvt_f32_u32_e32 v0, v0
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; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f16_to_i16_to_f16:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f16_e64 v1, |s2|
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; GFX9-NEXT: global_store_short v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui half %x to i16
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%fp = uitofp i16 %ui to half
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store half %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f16_to_i32_to_f16(ptr addrspace(1) %out, half %x) {
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; GFX6-LABEL: fptoui_f16_to_i32_to_f16:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_cvt_f32_f16_e64 v0, |s0|
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX6-NEXT: v_trunc_f32_e32 v0, v0
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; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f16_to_i32_to_f16:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f16_e64 v1, |s2|
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; GFX9-NEXT: global_store_short v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui half %x to i32
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%fp = uitofp i32 %ui to half
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store half %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f16_to_i64_to_f16(ptr addrspace(1) %out, half %x) {
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; GFX6-LABEL: fptoui_f16_to_i64_to_f16:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dword s0, s[4:5], 0xb
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_cvt_f32_f16_e64 v0, |s0|
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; GFX6-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX6-NEXT: v_trunc_f32_e32 v0, v0
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; GFX6-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: buffer_store_short v0, off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f16_to_i64_to_f16:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v0, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f16_e64 v1, |s2|
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; GFX9-NEXT: global_store_short v0, v1, s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui half %x to i64
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%fp = uitofp i64 %ui to half
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store half %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f64_to_i16_to_f64(ptr addrspace(1) %out, double %x) {
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; GFX6-LABEL: fptoui_f64_to_i16_to_f64:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_cvt_u32_f64_e32 v0, s[2:3]
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f64_to_i16_to_f64:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f64_e64 v[0:1], |s[2:3]|
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; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui double %x to i16
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%fp = uitofp i16 %ui to double
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store double %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f64_to_i32_to_f64(ptr addrspace(1) %out, double %x) {
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; GFX6-LABEL: fptoui_f64_to_i32_to_f64:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: v_cvt_u32_f64_e32 v0, s[2:3]
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; GFX6-NEXT: s_mov_b32 s3, 0xf000
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; GFX6-NEXT: s_mov_b32 s2, -1
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; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f64_to_i32_to_f64:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f64_e64 v[0:1], |s[2:3]|
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; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui double %x to i32
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%fp = uitofp i32 %ui to double
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store double %fp, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @fptoui_f64_to_i64_to_f64(ptr addrspace(1) %out, double %x) {
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; GFX6-LABEL: fptoui_f64_to_i64_to_f64:
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; GFX6: ; %bb.0: ; %entry
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; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
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; GFX6-NEXT: s_mov_b32 s6, -1
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; GFX6-NEXT: s_mov_b32 s5, 0xfffff
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; GFX6-NEXT: s_mov_b32 s4, s6
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; GFX6-NEXT: v_not_b32_e32 v0, 31
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; GFX6-NEXT: s_waitcnt lgkmcnt(0)
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; GFX6-NEXT: s_bfe_u32 s7, s3, 0xb0014
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; GFX6-NEXT: s_addk_i32 s7, 0xfc01
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; GFX6-NEXT: s_lshr_b64 s[4:5], s[4:5], s7
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; GFX6-NEXT: s_and_b32 s8, s3, 0x80000000
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; GFX6-NEXT: s_andn2_b64 s[4:5], s[2:3], s[4:5]
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; GFX6-NEXT: s_cmp_lt_i32 s7, 0
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; GFX6-NEXT: s_cselect_b32 s4, 0, s4
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; GFX6-NEXT: s_cselect_b32 s5, s8, s5
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; GFX6-NEXT: s_cmp_gt_i32 s7, 51
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; GFX6-NEXT: s_cselect_b32 s3, s3, s5
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; GFX6-NEXT: s_cselect_b32 s2, s2, s4
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; GFX6-NEXT: v_ldexp_f64 v[0:1], s[2:3], v0
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; GFX6-NEXT: v_mov_b32_e32 v4, -1
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; GFX6-NEXT: v_fract_f64_e32 v[2:3], v[0:1]
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; GFX6-NEXT: v_mov_b32_e32 v5, 0x3fefffff
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; GFX6-NEXT: v_min_f64 v[2:3], v[2:3], v[4:5]
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; GFX6-NEXT: v_cmp_class_f64_e64 vcc, v[0:1], 3
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; GFX6-NEXT: s_mov_b32 s4, 0
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; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc
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; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc
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; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], -v[2:3]
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; GFX6-NEXT: v_mov_b32_e32 v2, s2
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; GFX6-NEXT: s_mov_b32 s5, 0xc1f00000
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; GFX6-NEXT: v_mov_b32_e32 v3, s3
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; GFX6-NEXT: v_fma_f64 v[2:3], v[0:1], s[4:5], v[2:3]
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; GFX6-NEXT: v_cvt_u32_f64_e32 v0, v[0:1]
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; GFX6-NEXT: v_cvt_u32_f64_e32 v2, v[2:3]
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; GFX6-NEXT: s_mov_b32 s7, 0xf000
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; GFX6-NEXT: s_mov_b32 s4, s0
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; GFX6-NEXT: v_cvt_f64_u32_e32 v[0:1], v0
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; GFX6-NEXT: v_cvt_f64_u32_e32 v[2:3], v2
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; GFX6-NEXT: s_mov_b32 s5, s1
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; GFX6-NEXT: v_ldexp_f64 v[0:1], v[0:1], 32
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; GFX6-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3]
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; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
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; GFX6-NEXT: s_endpgm
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;
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; GFX9-LABEL: fptoui_f64_to_i64_to_f64:
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; GFX9: ; %bb.0: ; %entry
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
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; GFX9-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_trunc_f64_e64 v[0:1], |s[2:3]|
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; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
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; GFX9-NEXT: s_endpgm
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entry:
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%ui = fptoui double %x to i64
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%fp = uitofp i64 %ui to double
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store double %fp, ptr addrspace(1) %out
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ret void
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}
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