2b3e30d4c4
This prevents MachineSink from sinking loads past fences (or any other instruction marked as hasSideEffects). Fixes: #181708
68 lines
3.1 KiB
LLVM
68 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 < %s | FileCheck %s
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; iglp.opt should not be flagged as clobbering the memory operand for the global_load, and we should be able to
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; lower into the scalar version (i.e. should not need to lower into vector version with waterfall loop)
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define amdgpu_kernel void @func(ptr addrspace(1) %in, ptr addrspace(3) %out) {
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; CHECK-LABEL: func:
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; CHECK: ; %bb.0: ; %.lr.ph
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; CHECK-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x0
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; CHECK-NEXT: s_mov_b64 s[8:9], 0
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; CHECK-NEXT: s_mov_b32 s12, 32
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; CHECK-NEXT: s_mov_b32 s2, 0
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; CHECK-NEXT: s_mov_b64 s[0:1], s[8:9]
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; CHECK-NEXT: s_mov_b64 s[10:11], 0
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; CHECK-NEXT: .LBB0_1: ; %loop
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_and_b32 s1, s1, 0xffff
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; CHECK-NEXT: s_mov_b32 s3, s2
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; CHECK-NEXT: buffer_load_dwordx2 v[0:1], off, s[0:3], 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_add_u32 s0, s6, s10
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; CHECK-NEXT: s_addc_u32 s1, s7, s11
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; CHECK-NEXT: s_load_dwordx2 s[10:11], s[8:9], 0x0
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; CHECK-NEXT: s_add_i32 s12, s12, -1
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; CHECK-NEXT: s_cmp_lg_u32 s12, 0
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; CHECK-NEXT: ; iglp_opt mask(0x00000000)
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; CHECK-NEXT: s_cbranch_scc1 .LBB0_1
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; CHECK-NEXT: ; %bb.2: ; %end
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; CHECK-NEXT: s_load_dword s0, s[4:5], 0x8
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; CHECK-NEXT: s_waitcnt vmcnt(0)
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; CHECK-NEXT: v_and_b32_e32 v0, 0xff, v0
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_mov_b32_e32 v2, s0
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; CHECK-NEXT: ds_write_b64 v2, v[0:1]
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; CHECK-NEXT: s_endpgm
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.lr.ph:
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br label %loop
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loop: ; preds = %1, %.lr.ph
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%addr = phi ptr addrspace(1) [ null, %.lr.ph ], [ %gep, %loop ]
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%offset = phi i64 [ 0, %.lr.ph ], [ %nextOff, %loop ]
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%inc = phi i32 [0, %.lr.ph], [ %incCond, %loop ]
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%rsrc = tail call ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p1(ptr addrspace(1) %addr, i16 0, i64 0, i32 0)
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%load = tail call <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
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%load.bc = bitcast <2 x i32> %load to <8 x i8>
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%load.elem = extractelement <8 x i8> %load.bc, i64 0
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tail call void @llvm.amdgcn.iglp.opt(i32 0)
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%vec = insertelement <4 x i8> zeroinitializer, i8 %load.elem, i64 0
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%vec.bc = bitcast <4 x i8> %vec to <2 x half>
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%shuff = shufflevector <2 x half> %vec.bc, <2 x half> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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%gep = getelementptr i8, ptr addrspace(1) %in, i64 %offset
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%unmaskedload49 = load <1 x i64>, ptr addrspace(1) null, align 8
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%nextOff = extractelement <1 x i64> %unmaskedload49, i64 0
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%incCond = add i32 %inc, 1
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%cond = icmp eq i32 %incCond, 32
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br i1 %cond, label %end, label %loop
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end:
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store <4 x half> %shuff, ptr addrspace(3) %out, align 8
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ret void
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}
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declare ptr addrspace(8) @llvm.amdgcn.make.buffer.rsrc.p1(ptr addrspace(1) readnone, i16, i64, i32) #0
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declare <2 x i32> @llvm.amdgcn.raw.ptr.buffer.load.v2i32(ptr addrspace(8) nocapture readonly, i32, i32, i32 immarg) #1
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