5231736329
M0 can only be written to by the SALU, so `v_readfirstlane_b32 m0` is effectively useless. Represent this by restricting the dest RC of that instruction to `SReg_32_XM0` which excludes M0. There is a lot of test changes due to the register class changing, but most changes are trivial. In some cases, an extra register and `s_mov_b32` is needed. Fixes SWDEV-513269
48 lines
2.1 KiB
YAML
48 lines
2.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -run-pass=early-machinelicm,si-wqm -o - %s | FileCheck -check-prefix=GCN %s
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -passes=early-machinelicm,si-wqm -o - %s | FileCheck -check-prefix=GCN %s
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# Machine LICM may hoist an intruction from a WWM region, which will force SI-WQM pass
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# to create a second WWM region. This is an unwanted hoisting.
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---
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name: licm_move_wwm
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tracksRegLiveness: true
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body: |
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; GCN-LABEL: name: licm_move_wwm
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; GCN: bb.0:
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; GCN-NEXT: successors: %bb.1(0x80000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[ENTER_STRICT_WWM:%[0-9]+]]:sreg_32 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
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; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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; GCN-NEXT: $exec_lo = EXIT_STRICT_WWM [[ENTER_STRICT_WWM]]
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; GCN-NEXT: S_BRANCH %bb.1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.1:
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; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[ENTER_STRICT_WWM1:%[0-9]+]]:sreg_32 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
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; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[V_MOV_B32_e32_]], implicit $exec
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; GCN-NEXT: $exec_lo = EXIT_STRICT_WWM [[ENTER_STRICT_WWM1]]
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
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; GCN-NEXT: $exec_lo = S_OR_B32 $exec_lo, [[COPY]], implicit-def $scc
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; GCN-NEXT: S_CBRANCH_EXECNZ %bb.1, implicit $exec
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; GCN-NEXT: S_BRANCH %bb.2
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: bb.2:
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; GCN-NEXT: S_ENDPGM 0
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bb.0:
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S_BRANCH %bb.1
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bb.1:
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%0:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
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%1:sreg_32_xm0 = V_READFIRSTLANE_B32 killed %0:vgpr_32, implicit $exec
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early-clobber %2:sreg_32 = STRICT_WWM killed %1:sreg_32_xm0, implicit $exec
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$exec_lo = S_OR_B32 $exec_lo, %2, implicit-def $scc
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S_CBRANCH_EXECNZ %bb.1, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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S_ENDPGM 0
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...
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