40270e8ef2
Cover all the missing cases and add very detailed tests for each rule. In summary: - Flat and Scratch, addrspace(0) and addrspace(5), loads are always divergent. - Global and Constant, addrspace(1) and addrspace(4), have real uniform loads, s_load, but require additional checks for align and flags in mmo. For not natural align or not uniform mmo do uniform-in-vgpr lowering. - Private, addrspace(3), only has instructions for divergent load, for uniform do uniform-in-vgpr lowering. - Store rules are simplified using Ptr32 and Ptr64. All operands need to be vgpr. Some tests have code size regression since they use more sgpr instructions, marked with FixMe comment to get back to later.
70 lines
2.8 KiB
LLVM
70 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=ASM,DAGISEL-ASM
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=ASM,GISEL-ASM
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define void @local_to_flat(ptr addrspace(3) %ptr) {
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; ASM-LABEL: local_to_flat:
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; ASM: ; %bb.0:
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; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ASM-NEXT: s_mov_b64 s[4:5], src_shared_base
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; ASM-NEXT: v_mov_b32_e32 v1, s5
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; ASM-NEXT: v_mov_b32_e32 v2, 7
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; ASM-NEXT: flat_store_dword v[0:1], v2
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; ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; ASM-NEXT: s_setpc_b64 s[30:31]
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%1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3) %ptr)
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store volatile i32 7, ptr %1, align 4
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ret void
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}
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define void @private_to_flat(ptr addrspace(5) %ptr) {
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; ASM-LABEL: private_to_flat:
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; ASM: ; %bb.0:
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; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ASM-NEXT: s_mov_b64 s[4:5], src_private_base
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; ASM-NEXT: v_mov_b32_e32 v1, s5
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; ASM-NEXT: v_mov_b32_e32 v2, 7
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; ASM-NEXT: flat_store_dword v[0:1], v2
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; ASM-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; ASM-NEXT: s_setpc_b64 s[30:31]
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%1 = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %ptr)
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store volatile i32 7, ptr %1, align 4
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ret void
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}
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define void @flat_to_local(ptr %ptr) {
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; ASM-LABEL: flat_to_local:
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; ASM: ; %bb.0:
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; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ASM-NEXT: v_mov_b32_e32 v1, 7
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; ASM-NEXT: ds_write_b32 v0, v1
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; ASM-NEXT: s_waitcnt lgkmcnt(0)
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; ASM-NEXT: s_setpc_b64 s[30:31]
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%1 = call ptr addrspace(3) @llvm.amdgcn.addrspacecast.nonnull.p3.p0(ptr %ptr)
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store volatile i32 7, ptr addrspace(3) %1, align 4
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ret void
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}
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define void @flat_to_private(ptr %ptr) {
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; ASM-LABEL: flat_to_private:
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; ASM: ; %bb.0:
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; ASM-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; ASM-NEXT: v_mov_b32_e32 v1, 7
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; ASM-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
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; ASM-NEXT: s_waitcnt vmcnt(0)
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; ASM-NEXT: s_setpc_b64 s[30:31]
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%1 = call ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr %ptr)
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store volatile i32 7, ptr addrspace(5) %1, align 4
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ret void
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}
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declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p3(ptr addrspace(3))
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declare ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5))
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declare ptr addrspace(3) @llvm.amdgcn.addrspacecast.nonnull.p3.p0(ptr)
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declare ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr)
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declare <4 x ptr> @llvm.amdgcn.addrspacecast.nonnull.v4p0.v4p3(<4 x ptr addrspace(3)>)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; DAGISEL-ASM: {{.*}}
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; GISEL-ASM: {{.*}}
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