20e59c8e2d
Add RegBankLegalize rules for cube* intrinsics. Also update manual tests to use autogenerated checks.
31 lines
1.3 KiB
LLVM
31 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=GCN %s
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declare float @llvm.amdgcn.cubeid(float, float, float) #0
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define amdgpu_ps float @test_cubeid_vvv(float %a, float %b, float %c) #1 {
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; GCN-LABEL: test_cubeid_vvv:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_cubeid_f32 v0, v0, v1, v2
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; GCN-NEXT: ; return to shader part epilog
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%result = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
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ret float %result
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}
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define amdgpu_ps float @test_cubeid_sss(float inreg %a, float inreg %b, float inreg %c) #1 {
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; GCN-LABEL: test_cubeid_sss:
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; GCN: ; %bb.0:
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; GCN-NEXT: v_mov_b32_e32 v0, s1
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; GCN-NEXT: v_mov_b32_e32 v1, s2
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; GCN-NEXT: v_cubeid_f32 v0, s0, v0, v1
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; GCN-NEXT: ; return to shader part epilog
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%result = call float @llvm.amdgcn.cubeid(float %a, float %b, float %c)
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ret float %result
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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