5035d20dcb
These two instructions are supported by gfx1250. We define the instructions and implement the corresponding intrinsic and builtin. Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com>
22 lines
930 B
LLVM
22 lines
930 B
LLVM
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
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declare void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3))
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; GCN-LABEL: {{^}}test_ds_atomic_async_barrier_arrive_b64:
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; GCN: ds_atomic_async_barrier_arrive_b64 v0{{$}}
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define void @test_ds_atomic_async_barrier_arrive_b64(ptr addrspace(3) %bar) {
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entry:
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call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
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ret void
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}
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; GCN-LABEL: {{^}}test_ds_atomic_async_barrier_arrive_b64_off:
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; GCN: ds_atomic_async_barrier_arrive_b64 v0 offset:8184{{$}}
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define void @test_ds_atomic_async_barrier_arrive_b64_off(ptr addrspace(3) %in) {
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entry:
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%bar = getelementptr i64, ptr addrspace(3) %in, i32 1023
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call void @llvm.amdgcn.ds.atomic.async.barrier.arrive.b64(ptr addrspace(3) %bar)
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ret void
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}
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