6bf794a02a
Disable generic DAG combines for AMDGPU at -O0 via disableGenericCombines() to preserve instructions that users may want to set breakpoints on during debugging. Assisted-by: Cursor / Claude Opus 4.6
28 lines
1.4 KiB
LLVM
28 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -stop-after=postrapseudos -o - < %s | FileCheck -enable-var-scope -check-prefix=MIR %s
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define amdgpu_kernel void @gws_barrier_offset0(i32 %val) #0 {
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; MIR-LABEL: name: gws_barrier_offset0
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; MIR: bb.0 (%ir-block.0):
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; MIR-NEXT: liveins: $sgpr8_sgpr9
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; MIR-NEXT: {{ $}}
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; MIR-NEXT: dead renamable $sgpr4 = S_LOAD_DWORD_IMM renamable $sgpr8_sgpr9, 0, 0 :: (dereferenceable invariant load (s32) from constant-pool, align 16, addrspace 4)
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; MIR-NEXT: renamable $sgpr4 = S_LOAD_DWORD_IMM killed renamable $sgpr8_sgpr9, 0, 0 :: (dereferenceable invariant load (s32) from %ir.val.kernarg.offset, align 16, addrspace 4)
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; MIR-NEXT: $m0 = S_MOV_B32 0
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; MIR-NEXT: $vgpr0 = V_MOV_B32_e32 killed $sgpr4, implicit $exec, implicit $exec
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; MIR-NEXT: BUNDLE implicit killed renamable $vgpr0, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource") {
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; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load (s32) from custom "GWSResource")
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; MIR-NEXT: S_WAITCNT 0
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; MIR-NEXT: }
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; MIR-NEXT: S_ENDPGM 0
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call void @llvm.amdgcn.ds.gws.barrier(i32 %val, i32 0)
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ret void
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}
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declare void @llvm.amdgcn.ds.gws.barrier(i32, i32) #1
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attributes #0 = { nounwind }
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attributes #1 = { convergent inaccessiblememonly nounwind }
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