64 lines
2.6 KiB
LLVM
64 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=CHECK,GFX7 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,GFX8 %s
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=CHECK,GFX8 %s
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define amdgpu_kernel void @ds_swizzle(ptr addrspace(1) %out, i32 %src) nounwind {
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; GFX7-LABEL: ds_swizzle:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_load_dword s2, s[4:5], 0xb
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_mov_b32_e32 v0, s2
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; GFX7-NEXT: ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: ds_swizzle:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dword s2, s[4:5], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: ds_swizzle_b32 v2, v0 offset:swizzle(BITMASK_PERM,"00p11")
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; GFX8-NEXT: v_mov_b32_e32 v0, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s1
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100) #0
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store i32 %swizzle, ptr addrspace(1) %out, align 4
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ret void
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}
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define amdgpu_ps i32 @ds_swizzle_s(i32 inreg %src) {
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; CHECK-LABEL: ds_swizzle_s:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: v_mov_b32_e32 v0, s0
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; CHECK-NEXT: ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: ; return to shader part epilog
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%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100)
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ret i32 %swizzle
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}
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define amdgpu_ps i32 @ds_swizzle_v(i32 %src) {
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; CHECK-LABEL: ds_swizzle_v:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: ds_swizzle_b32 v0, v0 offset:swizzle(BITMASK_PERM,"00p11")
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: v_readfirstlane_b32 s0, v0
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; CHECK-NEXT: ; return to shader part epilog
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%swizzle = call i32 @llvm.amdgcn.ds.swizzle(i32 %src, i32 100)
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ret i32 %swizzle
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}
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declare i32 @llvm.amdgcn.ds.swizzle(i32, i32) #0
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attributes #0 = { nounwind readnone convergent }
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