2b4a462e95
The new format matches the official ISA spec and ensures the disassembler prints 'export mrt0, v0, off, off, off' instead of 'export mrt0 v0, off, off, off'. No functional encoding changes; printing/AsmString only.
18 lines
969 B
LLVM
18 lines
969 B
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=NOPRIM %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=PRIM %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=PRIM %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=PRIM %s
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declare void @llvm.amdgcn.exp.i32(i32, i32, i32, i32, i32, i32, i1, i1) #1
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; GCN-LABEL: {{^}}test_export_prim_i32:
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; NOPRIM: exp invalid_target_20, v0, off, off, off done{{$}}
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; PRIM: {{exp|export}} prim, v0, off, off, off done{{$}}
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define amdgpu_gs void @test_export_prim_i32(i32 inreg %a) #0 {
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call void @llvm.amdgcn.exp.i32(i32 20, i32 1, i32 %a, i32 poison, i32 poison, i32 poison, i1 true, i1 false)
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind inaccessiblememonly }
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