fa050eadab
(original PR: #166210) This allows more accurate alias analysis to apply at the bundle level. This has a bunch of minor effects in post-RA scheduling that look mostly beneficial to me, all of them in AMDGPU (the Thumb2 change is cosmetic). The pre-existing (and unchanged) test in CodeGen/MIR/AMDGPU/custom-pseudo-source-values.ll tests that MIR with a bundle with MMOs can be parsed successfully. v2: - use cloneMergedMemRefs - add another test to explicitly check the MMO bundling behavior v3: - use poison instead of undef to initialize the global variable in the test v4: - treat bundle memory accesses as never trivially disjoint
149 lines
7.6 KiB
LLVM
149 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-TRUE16
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,SDAG-GFX11,SDAG-GFX11-FAKE16
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-TRUE16
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; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck %s --check-prefixes=GFX11,GISEL-GFX11,GISEL-GFX11-FAKE16
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declare half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a, <2 x half> %b, half %c)
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define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f16_f16(
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; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
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; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry
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; SDAG-GFX11-TRUE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
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; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; SDAG-GFX11-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
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; SDAG-GFX11-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
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; SDAG-GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[6:7]
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; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; SDAG-GFX11-TRUE16-NEXT: v_dot2_f16_f16 v0.l, s2, s3, v0.l
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; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; SDAG-GFX11-TRUE16-NEXT: s_endpgm
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;
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; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
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; SDAG-GFX11-FAKE16: ; %bb.0: ; %entry
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; SDAG-GFX11-FAKE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
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; SDAG-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; SDAG-GFX11-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
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; SDAG-GFX11-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
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; SDAG-GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[6:7]
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; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; SDAG-GFX11-FAKE16-NEXT: v_dot2_f16_f16 v1, s2, s3, v1
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; SDAG-GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
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; SDAG-GFX11-FAKE16-NEXT: s_endpgm
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;
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; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
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; GISEL-GFX11-TRUE16: ; %bb.0: ; %entry
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; GISEL-GFX11-TRUE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
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; GISEL-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; GISEL-GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-GFX11-TRUE16-NEXT: s_load_b32 s2, s[2:3], 0x0
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; GISEL-GFX11-TRUE16-NEXT: s_load_b32 s3, s[4:5], 0x0
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; GISEL-GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[6:7]
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; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GISEL-GFX11-TRUE16-NEXT: v_dot2_f16_f16 v0.l, s2, s3, v0.l
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; GISEL-GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; GISEL-GFX11-TRUE16-NEXT: s_endpgm
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;
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; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16:
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; GISEL-GFX11-FAKE16: ; %bb.0: ; %entry
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; GISEL-GFX11-FAKE16-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
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; GISEL-GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0
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; GISEL-GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-GFX11-FAKE16-NEXT: s_load_b32 s2, s[2:3], 0x0
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; GISEL-GFX11-FAKE16-NEXT: s_load_b32 s3, s[4:5], 0x0
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; GISEL-GFX11-FAKE16-NEXT: global_load_u16 v1, v0, s[6:7]
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; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GISEL-GFX11-FAKE16-NEXT: v_dot2_f16_f16 v1, s2, s3, v1
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; GISEL-GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
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; GISEL-GFX11-FAKE16-NEXT: s_endpgm
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ptr addrspace(1) %r,
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ptr addrspace(1) %a,
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ptr addrspace(1) %b,
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ptr addrspace(1) %c) {
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entry:
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%a.val = load <2 x half>, ptr addrspace(1) %a
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%b.val = load <2 x half>, ptr addrspace(1) %b
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%c.val = load half, ptr addrspace(1) %c
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%r.val = call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a.val, <2 x half> %b.val, half %c.val)
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store half %r.val, ptr addrspace(1) %r
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ret void
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}
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define amdgpu_kernel void @test_llvm_amdgcn_fdot2_f16_f16_dpp(
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; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
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; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry
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; SDAG-GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; SDAG-GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; SDAG-GFX11-TRUE16-NEXT: scratch_load_b32 v1, off, s1
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; SDAG-GFX11-TRUE16-NEXT: scratch_load_b32 v2, off, s2
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; SDAG-GFX11-TRUE16-NEXT: scratch_load_d16_b16 v0, off, s3
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; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
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; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; SDAG-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; SDAG-GFX11-TRUE16-NEXT: v_dot2_f16_f16 v0.l, v1, v2, v0.l
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; SDAG-GFX11-TRUE16-NEXT: scratch_store_b16 off, v0, s0
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; SDAG-GFX11-TRUE16-NEXT: s_endpgm
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;
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; SDAG-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
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; SDAG-GFX11-FAKE16: ; %bb.0: ; %entry
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; SDAG-GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; SDAG-GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; SDAG-GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s2
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; SDAG-GFX11-FAKE16-NEXT: scratch_load_u16 v1, off, s3
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; SDAG-GFX11-FAKE16-NEXT: scratch_load_b32 v2, off, s1
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; SDAG-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; SDAG-GFX11-FAKE16-NEXT: v_dot2_f16_f16_e64_dpp v0, v2, v0, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; SDAG-GFX11-FAKE16-NEXT: scratch_store_b16 off, v0, s0
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; SDAG-GFX11-FAKE16-NEXT: s_endpgm
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;
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; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
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; GISEL-GFX11-TRUE16: ; %bb.0: ; %entry
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; GISEL-GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GISEL-GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-GFX11-TRUE16-NEXT: scratch_load_b32 v1, off, s1
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; GISEL-GFX11-TRUE16-NEXT: scratch_load_b32 v2, off, s2
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; GISEL-GFX11-TRUE16-NEXT: scratch_load_d16_b16 v0, off, s3
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; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(2)
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; GISEL-GFX11-TRUE16-NEXT: v_mov_b32_dpp v1, v1 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GISEL-GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
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; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GISEL-GFX11-TRUE16-NEXT: v_dot2_f16_f16 v0.l, v1, v2, v0.l
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; GISEL-GFX11-TRUE16-NEXT: scratch_store_b16 off, v0, s0
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; GISEL-GFX11-TRUE16-NEXT: s_endpgm
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;
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; GISEL-GFX11-FAKE16-LABEL: test_llvm_amdgcn_fdot2_f16_f16_dpp:
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; GISEL-GFX11-FAKE16: ; %bb.0: ; %entry
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; GISEL-GFX11-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
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; GISEL-GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
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; GISEL-GFX11-FAKE16-NEXT: scratch_load_b32 v0, off, s1
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; GISEL-GFX11-FAKE16-NEXT: scratch_load_b32 v1, off, s2
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; GISEL-GFX11-FAKE16-NEXT: scratch_load_u16 v2, off, s3
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; GISEL-GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
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; GISEL-GFX11-FAKE16-NEXT: v_dot2_f16_f16_e64_dpp v0, v0, v1, v2 quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:1
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; GISEL-GFX11-FAKE16-NEXT: scratch_store_b16 off, v0, s0
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; GISEL-GFX11-FAKE16-NEXT: s_endpgm
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ptr addrspace(5) %r,
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ptr addrspace(5) %a,
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ptr addrspace(5) %b,
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ptr addrspace(5) %c) {
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entry:
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%a.val = load <2 x half>, ptr addrspace(5) %a
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%b.val = load <2 x half>, ptr addrspace(5) %b
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%c.val = load half, ptr addrspace(5) %c
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%a.val.i32 = bitcast <2 x half> %a.val to i32
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%dpp = call i32 @llvm.amdgcn.update.dpp.i32(i32 %a.val.i32, i32 %a.val.i32, i32 1, i32 15, i32 15, i1 1)
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%a.val.dpp.v2half = bitcast i32 %dpp to <2 x half>
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%r.val = call half @llvm.amdgcn.fdot2.f16.f16(<2 x half> %a.val.dpp.v2half, <2 x half> %b.val, half %c.val)
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store half %r.val, ptr addrspace(5) %r
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ret void
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}
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declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1)
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX11: {{.*}}
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; GISEL-GFX11: {{.*}}
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; SDAG-GFX11: {{.*}}
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