d226f1b161
Regenerate checks after two recent commits that caused extra stuff to be added at the end of assembly lines, so the existing checks did not fail. - #179414 added "nv" to loads and stores on GFX1250. - #185774 added "msbs" comments on setreg instructions.
110 lines
4.4 KiB
LLVM
110 lines
4.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck --check-prefix=GCN %s
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declare void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 %col)
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define amdgpu_ps void @global_prefetch(ptr addrspace(1) %ptr) {
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; GCN-LABEL: global_prefetch:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v[0:1], off
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 0)
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ret void
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}
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define amdgpu_ps void @global_prefetch_sgpr(ptr addrspace(1) inreg %ptr) {
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; GCN-LABEL: global_prefetch_sgpr:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: global_prefetch_b8 v0, s[0:1]
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 0)
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ret void
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}
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define amdgpu_ps void @global_prefetch_offset(ptr addrspace(1) %ptr) {
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; GCN-LABEL: global_prefetch_offset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v[0:1], off offset:512
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; GCN-NEXT: s_endpgm
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entry:
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%gep = getelementptr inbounds i32, ptr addrspace(1) %ptr, i32 128
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %gep, i32 0)
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ret void
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}
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define amdgpu_ps void @global_prefetch_sgpr_voffset(ptr addrspace(1) inreg %ptr, i32 %offset) {
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; GCN-LABEL: global_prefetch_sgpr_voffset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v0, s[0:1]
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; GCN-NEXT: s_endpgm
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entry:
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%gep = getelementptr i8, ptr addrspace(1) %ptr, i32 %offset
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %gep, i32 0)
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ret void
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}
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define amdgpu_ps void @global_prefetch_sgpr_voffset_offset(ptr addrspace(1) inreg %ptr, i32 %offset) {
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; GCN-LABEL: global_prefetch_sgpr_voffset_offset:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v0, s[0:1] offset:128
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; GCN-NEXT: s_endpgm
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entry:
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%gep1 = getelementptr i8, ptr addrspace(1) %ptr, i32 %offset
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%gep2 = getelementptr i8, ptr addrspace(1) %gep1, i32 128
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %gep2, i32 0)
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ret void
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}
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define amdgpu_ps void @global_prefetch_se(ptr addrspace(1) %ptr) {
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; GCN-LABEL: global_prefetch_se:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v[0:1], off scope:SCOPE_SE
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 8)
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ret void
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}
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define amdgpu_ps void @global_prefetch_se_nt(ptr addrspace(1) %ptr) {
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; GCN-LABEL: global_prefetch_se_nt:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v[0:1], off th:TH_LOAD_NT scope:SCOPE_SE
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 9)
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ret void
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}
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define amdgpu_ps void @global_prefetch_dev_ht(ptr addrspace(1) %ptr) {
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; GCN-LABEL: global_prefetch_dev_ht:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v[0:1], off th:TH_LOAD_HT scope:SCOPE_DEV
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 18)
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ret void
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}
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define amdgpu_ps void @global_prefetch_sys_lu(ptr addrspace(1) %ptr) {
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; GCN-LABEL: global_prefetch_sys_lu:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GCN-NEXT: global_prefetch_b8 v[0:1], off th:TH_LOAD_BYPASS scope:SCOPE_SYS
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; GCN-NEXT: s_endpgm
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entry:
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tail call void @llvm.amdgcn.global.prefetch(ptr addrspace(1) %ptr, i32 27)
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ret void
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}
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