476a6ea957
Fix mfma agpr allocation failures with -O0. Previously we were getting lucky on cases that can use AV registers with the normal optimization pipeline. This logic needs to be consistent with getMaxNumVectorRegs, as that is what getReservedRegs to determine the AGPR budget. In the future we should directly check the minimum AGPR budget, and individual selection patterns need to know the minimum budget required for them. Start accounting for the number of AGPRs required to perform the allocation. Refine the selection predicates to check this number is available, and default to selecting the VGPR case if there aren't enough. This also avoids register allocation failures for the largest MFMAs with the default register budget.
278 lines
12 KiB
LLVM
278 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn -mcpu=gfx950 --amdgpu-mfma-vgpr-form=0 < %s | FileCheck -enable-var-scope --check-prefixes=HEURRC %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx950 --amdgpu-mfma-vgpr-form=1 < %s | FileCheck -enable-var-scope --check-prefixes=VGPRRC %s
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declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.f16(<8 x half>, <8 x half>, <4 x float>, i32 immarg, i32 immarg, i32 immarg)
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define <4 x float> @default(<8 x half> %arg0, <8 x half> %arg1, <4 x float> %arg2) {
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; HEURRC-LABEL: default:
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; HEURRC: ; %bb.0:
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; HEURRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; HEURRC-NEXT: v_accvgpr_write_b32 a0, v8
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; HEURRC-NEXT: v_accvgpr_write_b32 a1, v9
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; HEURRC-NEXT: v_accvgpr_write_b32 a2, v10
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; HEURRC-NEXT: v_accvgpr_write_b32 a3, v11
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; HEURRC-NEXT: s_nop 1
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; HEURRC-NEXT: v_mfma_f32_16x16x32_f16 a[0:3], v[0:3], v[4:7], a[0:3]
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; HEURRC-NEXT: s_nop 7
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; HEURRC-NEXT: v_accvgpr_read_b32 v0, a0
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; HEURRC-NEXT: v_accvgpr_read_b32 v1, a1
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; HEURRC-NEXT: v_accvgpr_read_b32 v2, a2
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; HEURRC-NEXT: v_accvgpr_read_b32 v3, a3
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; HEURRC-NEXT: s_setpc_b64 s[30:31]
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;
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; VGPRRC-LABEL: default:
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; VGPRRC: ; %bb.0:
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; VGPRRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VGPRRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[0:3], v[4:7], v[8:11]
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; VGPRRC-NEXT: s_setpc_b64 s[30:31]
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%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.f16(<8 x half> %arg0, <8 x half> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0)
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ret <4 x float> %result
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}
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define <4 x float> @request_agpr(<8 x half> %arg0, <8 x half> %arg1, <4 x float> %arg2) #0 {
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; HEURRC-LABEL: request_agpr:
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; HEURRC: ; %bb.0:
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; HEURRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; HEURRC-NEXT: v_accvgpr_write_b32 a0, v8
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; HEURRC-NEXT: v_accvgpr_write_b32 a1, v9
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; HEURRC-NEXT: v_accvgpr_write_b32 a2, v10
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; HEURRC-NEXT: v_accvgpr_write_b32 a3, v11
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; HEURRC-NEXT: s_nop 1
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; HEURRC-NEXT: v_mfma_f32_16x16x32_f16 a[0:3], v[0:3], v[4:7], a[0:3]
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; HEURRC-NEXT: s_nop 7
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; HEURRC-NEXT: v_accvgpr_read_b32 v0, a0
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; HEURRC-NEXT: v_accvgpr_read_b32 v1, a1
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; HEURRC-NEXT: v_accvgpr_read_b32 v2, a2
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; HEURRC-NEXT: v_accvgpr_read_b32 v3, a3
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; HEURRC-NEXT: s_setpc_b64 s[30:31]
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;
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; VGPRRC-LABEL: request_agpr:
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; VGPRRC: ; %bb.0:
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; VGPRRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VGPRRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[0:3], v[4:7], v[8:11]
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; VGPRRC-NEXT: s_setpc_b64 s[30:31]
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%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.f16(<8 x half> %arg0, <8 x half> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0)
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ret <4 x float> %result
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}
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define <4 x float> @request_no_agpr(<8 x half> %arg0, <8 x half> %arg1, <4 x float> %arg2) #1 {
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; HEURRC-LABEL: request_no_agpr:
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; HEURRC: ; %bb.0:
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; HEURRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; HEURRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[0:3], v[4:7], v[8:11]
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; HEURRC-NEXT: s_setpc_b64 s[30:31]
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;
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; VGPRRC-LABEL: request_no_agpr:
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; VGPRRC: ; %bb.0:
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; VGPRRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VGPRRC-NEXT: v_mfma_f32_16x16x32_f16 v[0:3], v[0:3], v[4:7], v[8:11]
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; VGPRRC-NEXT: s_setpc_b64 s[30:31]
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%result = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x32.f16(<8 x half> %arg0, <8 x half> %arg1, <4 x float> %arg2, i32 0, i32 0, i32 0)
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ret <4 x float> %result
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}
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; Make sure this selects the VGPR form, if AGPRs available, but not
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; enough.
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define amdgpu_kernel void @not_enough_agprs(ptr addrspace(1) %arg) #2 {
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; HEURRC-LABEL: not_enough_agprs:
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; HEURRC: ; %bb.0: ; %bb
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; HEURRC-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
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; HEURRC-NEXT: v_mov_b32_e32 v33, 1.0
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; HEURRC-NEXT: v_mov_b32_e32 v34, 2.0
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; HEURRC-NEXT: v_mov_b32_e32 v32, 0
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; HEURRC-NEXT: s_waitcnt lgkmcnt(0)
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; HEURRC-NEXT: s_load_dwordx16 s[16:31], s[34:35], 0x0
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; HEURRC-NEXT: s_load_dwordx16 s[0:15], s[34:35], 0x40
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; HEURRC-NEXT: s_waitcnt lgkmcnt(0)
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; HEURRC-NEXT: v_mov_b32_e32 v0, s16
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; HEURRC-NEXT: v_mov_b32_e32 v1, s17
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; HEURRC-NEXT: v_mov_b32_e32 v2, s18
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; HEURRC-NEXT: v_mov_b32_e32 v3, s19
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; HEURRC-NEXT: v_mov_b32_e32 v4, s20
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; HEURRC-NEXT: v_mov_b32_e32 v5, s21
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; HEURRC-NEXT: v_mov_b32_e32 v6, s22
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; HEURRC-NEXT: v_mov_b32_e32 v7, s23
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; HEURRC-NEXT: v_mov_b32_e32 v8, s24
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; HEURRC-NEXT: v_mov_b32_e32 v9, s25
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; HEURRC-NEXT: v_mov_b32_e32 v10, s26
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; HEURRC-NEXT: v_mov_b32_e32 v11, s27
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; HEURRC-NEXT: v_mov_b32_e32 v12, s28
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; HEURRC-NEXT: v_mov_b32_e32 v13, s29
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; HEURRC-NEXT: v_mov_b32_e32 v14, s30
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; HEURRC-NEXT: v_mov_b32_e32 v15, s31
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; HEURRC-NEXT: v_mov_b32_e32 v16, s0
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; HEURRC-NEXT: v_mov_b32_e32 v17, s1
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; HEURRC-NEXT: v_mov_b32_e32 v18, s2
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; HEURRC-NEXT: v_mov_b32_e32 v19, s3
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; HEURRC-NEXT: v_mov_b32_e32 v20, s4
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; HEURRC-NEXT: v_mov_b32_e32 v21, s5
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; HEURRC-NEXT: v_mov_b32_e32 v22, s6
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; HEURRC-NEXT: v_mov_b32_e32 v23, s7
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; HEURRC-NEXT: v_mov_b32_e32 v24, s8
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; HEURRC-NEXT: v_mov_b32_e32 v25, s9
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; HEURRC-NEXT: v_mov_b32_e32 v26, s10
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; HEURRC-NEXT: v_mov_b32_e32 v27, s11
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; HEURRC-NEXT: v_mov_b32_e32 v28, s12
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; HEURRC-NEXT: v_mov_b32_e32 v29, s13
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; HEURRC-NEXT: v_mov_b32_e32 v30, s14
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; HEURRC-NEXT: v_mov_b32_e32 v31, s15
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; HEURRC-NEXT: s_nop 1
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; HEURRC-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v33, v34, v[0:31] cbsz:1 abid:2 blgp:3
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; HEURRC-NEXT: s_nop 15
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; HEURRC-NEXT: s_nop 1
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; HEURRC-NEXT: global_store_dwordx4 v32, v[24:27], s[34:35] offset:96
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; HEURRC-NEXT: global_store_dwordx4 v32, v[28:31], s[34:35] offset:112
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; HEURRC-NEXT: global_store_dwordx4 v32, v[16:19], s[34:35] offset:64
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; HEURRC-NEXT: global_store_dwordx4 v32, v[20:23], s[34:35] offset:80
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; HEURRC-NEXT: global_store_dwordx4 v32, v[8:11], s[34:35] offset:32
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; HEURRC-NEXT: global_store_dwordx4 v32, v[12:15], s[34:35] offset:48
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; HEURRC-NEXT: global_store_dwordx4 v32, v[0:3], s[34:35]
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; HEURRC-NEXT: global_store_dwordx4 v32, v[4:7], s[34:35] offset:16
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; HEURRC-NEXT: s_endpgm
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;
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; VGPRRC-LABEL: not_enough_agprs:
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; VGPRRC: ; %bb.0: ; %bb
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; VGPRRC-NEXT: s_load_dwordx2 s[34:35], s[4:5], 0x24
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; VGPRRC-NEXT: v_mov_b32_e32 v33, 1.0
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; VGPRRC-NEXT: v_mov_b32_e32 v34, 2.0
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; VGPRRC-NEXT: v_mov_b32_e32 v32, 0
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; VGPRRC-NEXT: s_waitcnt lgkmcnt(0)
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; VGPRRC-NEXT: s_load_dwordx16 s[16:31], s[34:35], 0x0
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; VGPRRC-NEXT: s_load_dwordx16 s[0:15], s[34:35], 0x40
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; VGPRRC-NEXT: s_waitcnt lgkmcnt(0)
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; VGPRRC-NEXT: v_mov_b32_e32 v0, s16
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; VGPRRC-NEXT: v_mov_b32_e32 v1, s17
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; VGPRRC-NEXT: v_mov_b32_e32 v2, s18
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; VGPRRC-NEXT: v_mov_b32_e32 v3, s19
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; VGPRRC-NEXT: v_mov_b32_e32 v4, s20
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; VGPRRC-NEXT: v_mov_b32_e32 v5, s21
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; VGPRRC-NEXT: v_mov_b32_e32 v6, s22
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; VGPRRC-NEXT: v_mov_b32_e32 v7, s23
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; VGPRRC-NEXT: v_mov_b32_e32 v8, s24
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; VGPRRC-NEXT: v_mov_b32_e32 v9, s25
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; VGPRRC-NEXT: v_mov_b32_e32 v10, s26
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; VGPRRC-NEXT: v_mov_b32_e32 v11, s27
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; VGPRRC-NEXT: v_mov_b32_e32 v12, s28
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; VGPRRC-NEXT: v_mov_b32_e32 v13, s29
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; VGPRRC-NEXT: v_mov_b32_e32 v14, s30
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; VGPRRC-NEXT: v_mov_b32_e32 v15, s31
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; VGPRRC-NEXT: v_mov_b32_e32 v16, s0
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; VGPRRC-NEXT: v_mov_b32_e32 v17, s1
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; VGPRRC-NEXT: v_mov_b32_e32 v18, s2
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; VGPRRC-NEXT: v_mov_b32_e32 v19, s3
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; VGPRRC-NEXT: v_mov_b32_e32 v20, s4
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; VGPRRC-NEXT: v_mov_b32_e32 v21, s5
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; VGPRRC-NEXT: v_mov_b32_e32 v22, s6
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; VGPRRC-NEXT: v_mov_b32_e32 v23, s7
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; VGPRRC-NEXT: v_mov_b32_e32 v24, s8
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; VGPRRC-NEXT: v_mov_b32_e32 v25, s9
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; VGPRRC-NEXT: v_mov_b32_e32 v26, s10
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; VGPRRC-NEXT: v_mov_b32_e32 v27, s11
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; VGPRRC-NEXT: v_mov_b32_e32 v28, s12
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; VGPRRC-NEXT: v_mov_b32_e32 v29, s13
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; VGPRRC-NEXT: v_mov_b32_e32 v30, s14
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; VGPRRC-NEXT: v_mov_b32_e32 v31, s15
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; VGPRRC-NEXT: s_nop 1
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; VGPRRC-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v33, v34, v[0:31] cbsz:1 abid:2 blgp:3
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; VGPRRC-NEXT: s_nop 15
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; VGPRRC-NEXT: s_nop 1
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[24:27], s[34:35] offset:96
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[28:31], s[34:35] offset:112
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[16:19], s[34:35] offset:64
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[20:23], s[34:35] offset:80
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[8:11], s[34:35] offset:32
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[12:15], s[34:35] offset:48
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[0:3], s[34:35]
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; VGPRRC-NEXT: global_store_dwordx4 v32, v[4:7], s[34:35] offset:16
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; VGPRRC-NEXT: s_endpgm
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bb:
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%in.1 = load <32 x float>, ptr addrspace(1) %arg, align 128
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%mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %in.1, i32 1, i32 2, i32 3)
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store <32 x float> %mai.1, ptr addrspace(1) %arg, align 128
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ret void
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}
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define <16 x float> @mfma_scale_respect_flag(<8 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2, i32 %scale0, i32 %scale1) #2 {
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; HEURRC-LABEL: mfma_scale_respect_flag:
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; HEURRC: ; %bb.0:
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; HEURRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; HEURRC-NEXT: scratch_load_dword a15, off, s32
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; HEURRC-NEXT: scratch_load_dword v31, off, s32 offset:8
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; HEURRC-NEXT: scratch_load_dword v32, off, s32 offset:4
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; HEURRC-NEXT: v_accvgpr_write_b32 a0, v16
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; HEURRC-NEXT: v_accvgpr_write_b32 a1, v17
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; HEURRC-NEXT: v_accvgpr_write_b32 a2, v18
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; HEURRC-NEXT: v_accvgpr_write_b32 a3, v19
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; HEURRC-NEXT: v_accvgpr_write_b32 a4, v20
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; HEURRC-NEXT: v_accvgpr_write_b32 a5, v21
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; HEURRC-NEXT: v_accvgpr_write_b32 a6, v22
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; HEURRC-NEXT: v_accvgpr_write_b32 a7, v23
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; HEURRC-NEXT: v_accvgpr_write_b32 a8, v24
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; HEURRC-NEXT: v_accvgpr_write_b32 a9, v25
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; HEURRC-NEXT: v_accvgpr_write_b32 a10, v26
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; HEURRC-NEXT: v_accvgpr_write_b32 a11, v27
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; HEURRC-NEXT: v_accvgpr_write_b32 a12, v28
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; HEURRC-NEXT: v_accvgpr_write_b32 a13, v29
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; HEURRC-NEXT: v_accvgpr_write_b32 a14, v30
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; HEURRC-NEXT: s_waitcnt vmcnt(0)
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; HEURRC-NEXT: s_nop 0
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; HEURRC-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 a[0:15], v[0:7], v[8:15], a[0:15], v32, v31 op_sel_hi:[0,0,0]
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; HEURRC-NEXT: s_nop 15
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; HEURRC-NEXT: s_nop 3
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; HEURRC-NEXT: v_accvgpr_read_b32 v0, a0
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; HEURRC-NEXT: v_accvgpr_read_b32 v1, a1
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; HEURRC-NEXT: v_accvgpr_read_b32 v2, a2
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; HEURRC-NEXT: v_accvgpr_read_b32 v3, a3
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; HEURRC-NEXT: v_accvgpr_read_b32 v4, a4
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; HEURRC-NEXT: v_accvgpr_read_b32 v5, a5
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; HEURRC-NEXT: v_accvgpr_read_b32 v6, a6
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; HEURRC-NEXT: v_accvgpr_read_b32 v7, a7
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; HEURRC-NEXT: v_accvgpr_read_b32 v8, a8
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; HEURRC-NEXT: v_accvgpr_read_b32 v9, a9
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; HEURRC-NEXT: v_accvgpr_read_b32 v10, a10
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; HEURRC-NEXT: v_accvgpr_read_b32 v11, a11
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; HEURRC-NEXT: v_accvgpr_read_b32 v12, a12
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; HEURRC-NEXT: v_accvgpr_read_b32 v13, a13
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; HEURRC-NEXT: v_accvgpr_read_b32 v14, a14
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; HEURRC-NEXT: v_accvgpr_read_b32 v15, a15
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; HEURRC-NEXT: s_setpc_b64 s[30:31]
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;
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; VGPRRC-LABEL: mfma_scale_respect_flag:
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; VGPRRC: ; %bb.0:
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; VGPRRC-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; VGPRRC-NEXT: scratch_load_dword v31, off, s32
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; VGPRRC-NEXT: scratch_load_dword v32, off, s32 offset:8
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; VGPRRC-NEXT: scratch_load_dword v33, off, s32 offset:4
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; VGPRRC-NEXT: s_waitcnt vmcnt(0)
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; VGPRRC-NEXT: v_mfma_scale_f32_32x32x64_f8f6f4 v[16:31], v[0:7], v[8:15], v[16:31], v33, v32 op_sel_hi:[0,0,0]
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; VGPRRC-NEXT: s_nop 15
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; VGPRRC-NEXT: s_nop 3
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; VGPRRC-NEXT: v_mov_b32_e32 v0, v16
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; VGPRRC-NEXT: v_mov_b32_e32 v1, v17
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; VGPRRC-NEXT: v_mov_b32_e32 v2, v18
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; VGPRRC-NEXT: v_mov_b32_e32 v3, v19
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; VGPRRC-NEXT: v_mov_b32_e32 v4, v20
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; VGPRRC-NEXT: v_mov_b32_e32 v5, v21
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; VGPRRC-NEXT: v_mov_b32_e32 v6, v22
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; VGPRRC-NEXT: v_mov_b32_e32 v7, v23
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; VGPRRC-NEXT: v_mov_b32_e32 v8, v24
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; VGPRRC-NEXT: v_mov_b32_e32 v9, v25
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; VGPRRC-NEXT: v_mov_b32_e32 v10, v26
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; VGPRRC-NEXT: v_mov_b32_e32 v11, v27
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; VGPRRC-NEXT: v_mov_b32_e32 v12, v28
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; VGPRRC-NEXT: v_mov_b32_e32 v13, v29
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; VGPRRC-NEXT: v_mov_b32_e32 v14, v30
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; VGPRRC-NEXT: v_mov_b32_e32 v15, v31
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; VGPRRC-NEXT: s_setpc_b64 s[30:31]
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%result = call <16 x float> @llvm.amdgcn.mfma.scale.f32.32x32x64.f8f6f4.v8i32.v8i32(<8 x i32> %arg0, <8 x i32> %arg1, <16 x float> %arg2,
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i32 0, ; cbsz
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i32 0, ; blgp
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i32 0, i32 %scale0, i32 0, i32 %scale1)
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ret <16 x float> %result
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|
}
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|
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attributes #0 = { "amdgpu-agpr-alloc"="32,256" }
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attributes #1 = { "amdgpu-agpr-alloc"="0,0" }
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attributes #2 = { nounwind "amdgpu-agpr-alloc"="20" }
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