4cba4ad8d7
Merge rule with groupstaticsize, also change to use fast uniform rule since both of these intrinsics are uniform with no inputs.
186 lines
7.1 KiB
LLVM
186 lines
7.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GFX9,SDAG,GFX9-SDAG
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefixes=GFX9,GFX9-GISEL
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10,SDAG,GFX10-SDAG
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; RUN: llc -global-isel=1 -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck %s -check-prefixes=GFX10,GFX10-GISEL
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declare void @foo(i32)
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define amdgpu_ps void @test(ptr addrspace(1) inreg %ptr) {
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; SDAG-LABEL: test:
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; SDAG: ; %bb.0:
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; SDAG-NEXT: s_mov_b32 s2, src_pops_exiting_wave_id
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; SDAG-NEXT: v_mov_b32_e32 v0, 0
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; SDAG-NEXT: v_mov_b32_e32 v1, s2
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; SDAG-NEXT: global_store_dword v0, v1, s[0:1]
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; SDAG-NEXT: s_endpgm
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;
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; GFX9-GISEL-LABEL: test:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_mov_b32 s2, src_pops_exiting_wave_id
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX9-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX9-GISEL-NEXT: s_endpgm
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;
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; GFX10-GISEL-LABEL: test:
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; GFX10-GISEL: ; %bb.0:
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; GFX10-GISEL-NEXT: s_mov_b32 s2, src_pops_exiting_wave_id
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; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
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; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s2
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; GFX10-GISEL-NEXT: global_store_dword v1, v0, s[0:1]
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; GFX10-GISEL-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.pops.exiting.wave.id()
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store i32 %id, ptr addrspace(1) %ptr
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ret void
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}
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define amdgpu_ps void @test_loop() {
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; GFX9-LABEL: test_loop:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: .LBB1_1: ; %loop
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; GFX9-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX9-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX9-NEXT: s_cmp_eq_u32 s0, 0
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; GFX9-NEXT: s_cbranch_scc1 .LBB1_1
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; GFX9-NEXT: ; %bb.2: ; %exit
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; GFX9-NEXT: s_endpgm
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;
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; GFX10-LABEL: test_loop:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: .LBB1_1: ; %loop
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; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
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; GFX10-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX10-NEXT: s_cmp_eq_u32 s0, 0
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; GFX10-NEXT: s_cbranch_scc1 .LBB1_1
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; GFX10-NEXT: ; %bb.2: ; %exit
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; GFX10-NEXT: s_endpgm
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br label %loop
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loop:
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%id = call i32 @llvm.amdgcn.pops.exiting.wave.id()
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%cond = icmp eq i32 %id, 0
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br i1 %cond, label %loop, label %exit
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exit:
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ret void
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}
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define amdgpu_ps i32 @test_if(i1 inreg %cond) {
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; SDAG-LABEL: test_if:
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; SDAG: ; %bb.0: ; %entry
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; SDAG-NEXT: s_bitcmp0_b32 s0, 0
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; SDAG-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; SDAG-NEXT: s_cbranch_scc1 .LBB2_2
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; SDAG-NEXT: ; %bb.1: ; %body
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; SDAG-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; SDAG-NEXT: .LBB2_2: ; %exit
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; SDAG-NEXT: ; return to shader part epilog
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;
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; GFX9-GISEL-LABEL: test_if:
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; GFX9-GISEL: ; %bb.0: ; %entry
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; GFX9-GISEL-NEXT: s_mov_b32 s1, s0
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; GFX9-GISEL-NEXT: s_xor_b32 s1, s1, 1
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; GFX9-GISEL-NEXT: s_and_b32 s1, s1, 1
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; GFX9-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX9-GISEL-NEXT: s_cmp_lg_u32 s1, 0
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; GFX9-GISEL-NEXT: s_cbranch_scc1 .LBB2_2
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; GFX9-GISEL-NEXT: ; %bb.1: ; %body
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; GFX9-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX9-GISEL-NEXT: .LBB2_2: ; %exit
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; GFX9-GISEL-NEXT: ; return to shader part epilog
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;
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; GFX10-GISEL-LABEL: test_if:
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; GFX10-GISEL: ; %bb.0: ; %entry
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; GFX10-GISEL-NEXT: s_xor_b32 s0, s0, 1
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; GFX10-GISEL-NEXT: s_and_b32 s1, s0, 1
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; GFX10-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX10-GISEL-NEXT: s_cmp_lg_u32 s1, 0
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; GFX10-GISEL-NEXT: s_cbranch_scc1 .LBB2_2
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; GFX10-GISEL-NEXT: ; %bb.1: ; %body
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; GFX10-GISEL-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX10-GISEL-NEXT: .LBB2_2: ; %exit
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; GFX10-GISEL-NEXT: ; return to shader part epilog
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entry:
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%id1 = call i32 @llvm.amdgcn.pops.exiting.wave.id()
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br i1 %cond, label %body, label %exit
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body:
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%id2 = call i32 @llvm.amdgcn.pops.exiting.wave.id()
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br label %exit
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exit:
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%id = phi i32 [ %id1, %entry ], [ %id2, %body ]
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ret i32 %id
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}
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define amdgpu_ps void @test_call(ptr addrspace(1) inreg %ptr) {
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; GFX9-SDAG-LABEL: test_call:
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; GFX9-SDAG: ; %bb.0:
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; GFX9-SDAG-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
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; GFX9-SDAG-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
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; GFX9-SDAG-NEXT: s_mov_b32 s38, -1
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; GFX9-SDAG-NEXT: s_mov_b32 s39, 0xe00000
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; GFX9-SDAG-NEXT: s_add_u32 s36, s36, s2
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; GFX9-SDAG-NEXT: s_addc_u32 s37, s37, 0
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; GFX9-SDAG-NEXT: s_getpc_b64 s[0:1]
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; GFX9-SDAG-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
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; GFX9-SDAG-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
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; GFX9-SDAG-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
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; GFX9-SDAG-NEXT: s_mov_b32 s6, src_pops_exiting_wave_id
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; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[36:37]
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; GFX9-SDAG-NEXT: s_mov_b64 s[8:9], 36
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; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[38:39]
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s6
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; GFX9-SDAG-NEXT: s_mov_b32 s32, 0
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; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GFX9-SDAG-NEXT: s_endpgm
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;
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; GFX9-GISEL-LABEL: test_call:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
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; GFX9-GISEL-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
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; GFX9-GISEL-NEXT: s_mov_b32 s38, -1
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; GFX9-GISEL-NEXT: s_mov_b32 s39, 0xe00000
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; GFX9-GISEL-NEXT: s_add_u32 s36, s36, s2
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; GFX9-GISEL-NEXT: s_addc_u32 s37, s37, 0
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; GFX9-GISEL-NEXT: s_getpc_b64 s[0:1]
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; GFX9-GISEL-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
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; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
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; GFX9-GISEL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
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; GFX9-GISEL-NEXT: s_mov_b32 s2, src_pops_exiting_wave_id
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s2
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; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[36:37]
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; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[38:39]
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; GFX9-GISEL-NEXT: s_mov_b64 s[8:9], 36
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; GFX9-GISEL-NEXT: s_mov_b32 s32, 0
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; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GFX9-GISEL-NEXT: s_endpgm
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;
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; GFX10-LABEL: test_call:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_mov_b32 s36, SCRATCH_RSRC_DWORD0
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; GFX10-NEXT: s_mov_b32 s37, SCRATCH_RSRC_DWORD1
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; GFX10-NEXT: s_mov_b32 s38, -1
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; GFX10-NEXT: s_mov_b32 s39, 0x31c16000
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; GFX10-NEXT: s_add_u32 s36, s36, s2
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; GFX10-NEXT: s_addc_u32 s37, s37, 0
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; GFX10-NEXT: s_getpc_b64 s[0:1]
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; GFX10-NEXT: s_add_u32 s0, s0, foo@gotpcrel32@lo+4
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; GFX10-NEXT: s_addc_u32 s1, s1, foo@gotpcrel32@hi+12
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; GFX10-NEXT: s_mov_b64 s[8:9], 36
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; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
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; GFX10-NEXT: s_mov_b32 s0, src_pops_exiting_wave_id
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; GFX10-NEXT: s_mov_b32 s32, 0
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; GFX10-NEXT: v_mov_b32_e32 v0, s0
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; GFX10-NEXT: s_mov_b64 s[0:1], s[36:37]
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; GFX10-NEXT: s_mov_b64 s[2:3], s[38:39]
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
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; GFX10-NEXT: s_endpgm
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%id = call i32 @llvm.amdgcn.pops.exiting.wave.id()
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call void @foo(i32 %id)
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ret void
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; GFX10-SDAG: {{.*}}
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