d226f1b161
Regenerate checks after two recent commits that caused extra stuff to be added at the end of assembly lines, so the existing checks did not fail. - #179414 added "nv" to loads and stores on GFX1250. - #185774 added "msbs" comments on setreg instructions.
110 lines
5.1 KiB
LLVM
110 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefix=SDAG-TRUE16 %s
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; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefix=SDAG-FAKE16 %s
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; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=+real-true16 < %s | FileCheck -check-prefix=GI-TRUE16 %s
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; xUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1250 -mattr=-real-true16 < %s | FileCheck -check-prefix=GI-FAKE16 %s
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; FIXME: GlobalISel does not work with bf16
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declare bfloat @llvm.amdgcn.rcp.bf16(bfloat) #0
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define amdgpu_kernel void @rcp_bf16(ptr addrspace(1) %out, bfloat %src) #1 {
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; SDAG-TRUE16-LABEL: rcp_bf16:
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; SDAG-TRUE16: ; %bb.0:
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; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-TRUE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0 nv
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; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-TRUE16-NEXT: v_rcp_bf16_e32 v0.l, s2
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; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; SDAG-TRUE16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: rcp_bf16:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_load_b96 s[0:2], s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: v_rcp_bf16_e32 v0, s2
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; SDAG-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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%rcp = call bfloat @llvm.amdgcn.rcp.bf16(bfloat %src) #0
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store bfloat %rcp, ptr addrspace(1) %out, align 2
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ret void
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}
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define amdgpu_kernel void @rcp_bf16_constant_4(ptr addrspace(1) %out) #1 {
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; SDAG-TRUE16-LABEL: rcp_bf16_constant_4:
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; SDAG-TRUE16: ; %bb.0:
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; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3e80
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; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; SDAG-TRUE16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: rcp_bf16_constant_4:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3e80
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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%rcp = call bfloat @llvm.amdgcn.rcp.bf16(bfloat 4.0) #0
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store bfloat %rcp, ptr addrspace(1) %out, align 2
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ret void
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}
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define amdgpu_kernel void @rcp_bf16_constant_100(ptr addrspace(1) %out) #1 {
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; SDAG-TRUE16-LABEL: rcp_bf16_constant_100:
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; SDAG-TRUE16: ; %bb.0:
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; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3c24
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; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; SDAG-TRUE16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: rcp_bf16_constant_100:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x3c24
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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%rcp = call bfloat @llvm.amdgcn.rcp.bf16(bfloat 100.0) #0
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store bfloat %rcp, ptr addrspace(1) %out, align 2
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ret void
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}
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define amdgpu_kernel void @rcp_undef_bf16(ptr addrspace(1) %out) #1 {
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; SDAG-TRUE16-LABEL: rcp_undef_bf16:
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; SDAG-TRUE16: ; %bb.0:
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; SDAG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
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; SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x7fc0
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; SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
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; SDAG-TRUE16-NEXT: s_endpgm
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;
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; SDAG-FAKE16-LABEL: rcp_undef_bf16:
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; SDAG-FAKE16: ; %bb.0:
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; SDAG-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; SDAG-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 nv
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; SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0x7fc0
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; SDAG-FAKE16-NEXT: s_wait_kmcnt 0x0
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; SDAG-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
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; SDAG-FAKE16-NEXT: s_endpgm
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%rcp = call bfloat @llvm.amdgcn.rcp.bf16(bfloat undef)
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store bfloat %rcp, ptr addrspace(1) %out, align 2
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ret void
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}
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind }
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