353b5e43c6
Let's do the lowering of non-split into split barriers in a new IR pass, AMDGPULowerIntrinsics. That way, there is no code duplication between SelectionDAG and GlobalISel. This simplifies some upcoming extensions to the code.
81 lines
3.7 KiB
LLVM
81 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=0 | FileCheck --check-prefixes=CHECK,NOOPT %s
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; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=1 -mattr=+wavefrontsize32 | FileCheck --check-prefixes=CHECK,OPT-WAVE32 %s
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; RUN: opt < %s -passes=amdgpu-lower-intrinsics -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 -codegen-opt-level=1 -mattr=+wavefrontsize64 | FileCheck --check-prefixes=CHECK,OPT-WAVE64 %s
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declare void @foo(i1)
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define amdgpu_kernel void @barrier() {
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; CHECK-LABEL: define amdgpu_kernel void @barrier(
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; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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; CHECK-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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; CHECK-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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; CHECK-NEXT: call void @foo(i1 [[ISFIRST]])
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; CHECK-NEXT: ret void
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;
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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call void @foo(i1 %isfirst)
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ret void
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}
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define amdgpu_kernel void @barrier_32threads() "amdgpu-flat-work-group-size"="32,32" {
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; NOOPT-LABEL: define amdgpu_kernel void @barrier_32threads(
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; NOOPT-SAME: ) #[[ATTR1:[0-9]+]] {
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; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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; NOOPT-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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; NOOPT-NEXT: call void @foo(i1 [[ISFIRST]])
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; NOOPT-NEXT: ret void
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;
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; OPT-WAVE32-LABEL: define amdgpu_kernel void @barrier_32threads(
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; OPT-WAVE32-SAME: ) #[[ATTR1:[0-9]+]] {
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; OPT-WAVE32-NEXT: call void @llvm.amdgcn.wave.barrier()
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; OPT-WAVE32-NEXT: call void @foo(i1 true)
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; OPT-WAVE32-NEXT: ret void
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;
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; OPT-WAVE64-LABEL: define amdgpu_kernel void @barrier_32threads(
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; OPT-WAVE64-SAME: ) #[[ATTR1:[0-9]+]] {
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; OPT-WAVE64-NEXT: call void @llvm.amdgcn.wave.barrier()
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; OPT-WAVE64-NEXT: call void @foo(i1 true)
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; OPT-WAVE64-NEXT: ret void
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;
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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call void @foo(i1 %isfirst)
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ret void
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}
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define amdgpu_kernel void @barrier_64threads() "amdgpu-flat-work-group-size"="64,64" {
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; NOOPT-LABEL: define amdgpu_kernel void @barrier_64threads(
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; NOOPT-SAME: ) #[[ATTR2:[0-9]+]] {
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; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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; NOOPT-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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; NOOPT-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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; NOOPT-NEXT: call void @foo(i1 [[ISFIRST]])
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; NOOPT-NEXT: ret void
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;
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; OPT-WAVE32-LABEL: define amdgpu_kernel void @barrier_64threads(
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; OPT-WAVE32-SAME: ) #[[ATTR2:[0-9]+]] {
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; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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; OPT-WAVE32-NEXT: call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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; OPT-WAVE32-NEXT: [[ISFIRST:%.*]] = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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; OPT-WAVE32-NEXT: call void @foo(i1 [[ISFIRST]])
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; OPT-WAVE32-NEXT: ret void
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;
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; OPT-WAVE64-LABEL: define amdgpu_kernel void @barrier_64threads(
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; OPT-WAVE64-SAME: ) #[[ATTR2:[0-9]+]] {
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; OPT-WAVE64-NEXT: call void @llvm.amdgcn.wave.barrier()
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; OPT-WAVE64-NEXT: call void @foo(i1 true)
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; OPT-WAVE64-NEXT: ret void
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;
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call void @llvm.amdgcn.s.barrier.signal(i32 -1)
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call void @llvm.amdgcn.s.barrier.wait(i16 -1)
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%isfirst = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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call void @foo(i1 %isfirst)
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ret void
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}
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